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研究生： 古孝澤
SHIAU-TZA GU
論文名稱： 具3.9微微秒解析度之自我校準式時間至數位轉換電路
Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution
指導教授： 陳伯奇
Poki Chen
口試委員: 陳信樹
Hsin-Shu Chen
陳筱青
Hsiao-Chin Chen
黃育賢
Yuh-Shyan Hwang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 中文
論文頁數： 97
中文關鍵詞： 時間至數位轉換器 、脈衝擴展器 、雙斜率法 、自我校準
外文關鍵詞： Time-to-Digital Converter(TDC), Pulse Stretcher, Dual Slope, Self-Calibration
相關次數： 點閱：245  下載：5 
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    • 　　本論文為一個具有自我校準功能並以脈衝擴展法為基礎之時間至數位轉換器，脈衝擴展器以雙斜率法實現，並搭配循序漸進暫存器達到自我校準的功能，以降低環境溫度、製程參數、工作電壓等環境變異所造成之誤差，使脈衝擴展法時間至數位轉換器的量測精準度不易受到周圍環境的改變而變化。
    　　本時間至數位轉換器之解析度高達3.9ps，核心電路面積為0.77×0.25 mm2，消耗功率為15.4mW，以TSMC 1P6M 0.18μm的製程實現，模擬結果指出，在五個製程參數變異、電壓變異1.62V到1.98V與溫度變異0℃到100℃的環境下皆可藉由自我校準功能將擴展因子調整至預期規格需求。

    This paper provides a TDC based on pulse stretch method possesses self calibration technique. The pulse stretcher is implemented by dual-slope method. The self calibration technique uses Successive-Approximation Register (SAR) to reduce the error from process, supply voltage and ambient temperature (PVT) variation. Therefore, the precision and accuracy have low sensitivity of PVT variation.
    The resolution of proposed TDC reaches 3.9ps. Die area is 0.77×0.25 mm2. The power consumption is 15.4mW. The process is TSMC 1P6M 0.18μm. According to the simulation result, under process variation, supply voltage variation over 1.62V to 1.98V and ambient temperature variation over 0℃ to 100℃, the stretch factor tallies the requirement of anticipated specification.

    目錄 中文摘要………………………………………………………………………I 英文摘要………………………………………………………………………II 誌　　謝………………………………………………………………………III 目　　錄………………………………………………………………………IV 圖 目 錄………………………………………………………………………VII 表 目 錄………………………………………………………………………XI 第一章 緒論…………………………………………………………………….1 1.1 研究動機……………………………………………………………………1 1.2 內容編排方式………………………………………………………………3 第二章 時間至數位轉換器…………………………………………………….4 2.1 時間至數位轉換器簡介……………………………………………………4 2.2 計數器法之時間至數位轉換器……………………………………………5 2.3 脈衝縮減延遲法之時間至數位轉換器……………………………………8 2.3.1 線性脈衝延遲法……………………………………8 2.3.2 循環式脈衝縮減法…………………………………9 2.3.3　非均質與均質脈衝縮減延遲線…………………10 2.4 場可程式化閘陣列為主體之時間至數位轉換器……………………….12 2.5 游標卡尺法之時間至數位轉換器……………………………………….15 第三章 具3.9微微秒解析度之自我校準式時間至數位轉換器…………….19 3.1脈衝擴展法之時間至數位轉換器…………………………………………20 3.2具3.9微微秒解析度之自我校準式時間至數位轉換器………………….22 3.3時間至脈衝控制電路………………………………………………………23 3.3.1時間至脈衝控制電路介紹…………………………23 3.3.2介穩態………………………………………………27 3.4脈衝擴展器(內插器)………………………………………………………30 3.5具3.9微微秒解析度之自我校準式脈衝擴展器………………………….34 3.5.1自我校準式脈衝擴展器工作原理…………………34 3.5.2內插器開關切換之誤差……………………………38 3.5.3放電電容間之寄生耦合電容………………………43 3.5.3.1放電電容間耦合電容之解決方法………………43 3.5.4有限的電流源輸出阻抗……………………………45 3.5.5循序漸進暫存器(SAR)…………………………….47 3.5.6比較器………………………………………………50 3.5.6.1比較器概論………………………………………50 3.5.6.2比較器原理說明…………………………………51 3.5.6.3比較器之架構……………………………………55 3.5.7計數器………………………………………………58 第四章 電路模擬與晶片佈局…………………………………………………59 4.1設計流程與考量……………………………………………………………59 4.2具3.9微微秒解析度之自我校準式時間至數位轉換器模擬及驗證……………………………………………………………………………….61 4.2.1時間至脈衝控制電路模擬…………………………62 4.2.2循序漸進暫存器(SAR)模擬……………………….64 4.2.3具自我校準之脈衝擴展器模擬……………………66 4.2.4比較器模擬…………………………………………72 4.2.5計數器模擬…………………………………………74 4.2.6時間至數位轉換器系統模擬………………………75 4.3 晶片佈局…………………………………………………………….80 第五章 量測考量………………………………………………………………82 5.1量測環境……………………………………………………………………82 5.2量測方法……………………………………………………………………85 第六章 結論與未來展望………………………………………………………88 6.1 文獻比較………………………………………………………………….88 6.2 未來展望………………………………………………………………….90 參考文獻……………………………………………………………………...92

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