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研究生: 郭柏甫
Bo-Fu Kuo
論文名稱: Weak-Page-Based Static Wear Leveling for Flash Memory Storage Systems
Weak-Page-Based Static Wear Leveling for Flash Memory Storage Systems
指導教授: 謝仁偉
Jen-Wei Hsieh
口試委員: 吳晉賢
Chin-Hsien Wu
陳雅淑
Ya-Shu Chen
修丕承
Pi-Cheng Hsiu
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 英文
論文頁數: 42
中文關鍵詞: 固態硬碟抹除均衡
外文關鍵詞: bit error rates
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In recent year, NAND flash memory has been widely used as primary storage medium such as embedded systems, portable devices, and high-performance storage products, the reasons including its non-volatility, lightweight, high performance, low power consumption and shock resistance. As the improvement of manufacturing technology, the cost per unit of NAND flash memory has been fast decrease. However, the program/erase (P/E) cycles of flash memory also keep decreasing since the density of NAND flash memory increasing. Thus, to improve the lifetime of flash memory has become a critical issue in the design of flash-based products. In NAND flash-based solid state driver (SSD), wear leveling is used to prolong the device lifetime. Its algorithm try to distribute the erase to flash block evenly since the flash memory can only endure a limited number of P/E cycles. In this paper, we distribute the bit error rates (BER) instead of P/E cycle. This work is inspired of observation of flash blocks endured the same P/E cycles usually have a different number of error bits. Since the main reason of flash block failure depend on the uncorrectable error in a page with ECC. This paper try to even out the BER based on the identification of number of weak pages in a flash block. The experiments shows that the proposed mechanism can efficiently prolong the lifetime by balancing the weak pages among flash blocks. It improves the lifetime of total device failed by up to 67\% in general workloads. For performance concern, weak-page-based wear leveling bring acceptable performance overhead in read response time. These results shows that weak-page-based wear leveling is better to use for the applications which need to achieving higher reliability.


In recent year, NAND flash memory has been widely used as primary storage medium such as embedded systems, portable devices, and high-performance storage products, the reasons including its non-volatility, lightweight, high performance, low power consumption and shock resistance. As the improvement of manufacturing technology, the cost per unit of NAND flash memory has been fast decrease. However, the program/erase (P/E) cycles of flash memory also keep decreasing since the density of NAND flash memory increasing. Thus, to improve the lifetime of flash memory has become a critical issue in the design of flash-based products. In NAND flash-based solid state driver (SSD), wear leveling is used to prolong the device lifetime. Its algorithm try to distribute the erase to flash block evenly since the flash memory can only endure a limited number of P/E cycles. In this paper, we distribute the bit error rates (BER) instead of P/E cycle. This work is inspired of observation of flash blocks endured the same P/E cycles usually have a different number of error bits. Since the main reason of flash block failure depend on the uncorrectable error in a page with ECC. This paper try to even out the BER based on the identification of number of weak pages in a flash block. The experiments shows that the proposed mechanism can efficiently prolong the lifetime by balancing the weak pages among flash blocks. It improves the lifetime of total device failed by up to 67\% in general workloads. For performance concern, weak-page-based wear leveling bring acceptable performance overhead in read response time. These results shows that weak-page-based wear leveling is better to use for the applications which need to achieving higher reliability.

1 Introduction 5 2 Background and Motivation 8 2.1 NAND Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Wear Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Weak-Page-based Wear Leveling 16 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 Garbage Collector . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.2 Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 Wear Leveler . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Weak-Page Management Scheme . . . . . . . . . . . . . . . . . . 20 3.3.1 Weak Page . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.2 Weak-Page Table . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.3 Adaptive Weak Page Threshold . . . . . . . . . . . . . . . 21 3.3.4 Update Process of WPT . . . . . . . . . . . . . . . . . . . 21 3.4 Weak-Page-Based Wear Leveling . . . . . . . . . . . . . . . . . . 22 3.4.1 Static wear leveling threshold . . . . . . . . . . . . . . . . 23 3.4.2 Victim Block Selection . . . . . . . . . . . . . . . . . . . . 23 3.4.3 Static Wear Leveling Procedure . . . . . . . . . . . . . . . 24 4 Experiments 26 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 Lifetime Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 Response Time . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 Management Overhead . . . . . . . . . . . . . . . . . . . . 35 4.3.3 Space Overhead of WPT . . . . . . . . . . . . . . . . . . . 36 5 Conclusion 40

[1] X. Jimenez, D. Novo, and P. Ienne., “Wear unleveling: improving
nand flash lifetime by balancing page endurance.” In Proceedings of the 12th USENIX conference on File and Storage Technologies(FAST), pp. 47–59, 2014.
[2] Y. Pan, G. Dong, and T. Zhang., “Exploiting memory device
wear-out dynamics to improve nand flash memory system performance.”
In Proceedings of the 9th USENIX conference on File and
Storage Technologies(FAST), pp. 18 – 18, 2011.
[3] “http://flashdba.com/2014/07/03/understanding-flash-slc-mlcand-
tlc/.”
[4] X.-Y. Hu, E. Eleftheriou, R. Haas, I. Iliadis, and R. Pletka, “Write
amplification analysis in flash-based solid state drives,” in Proceedings
of SYSTOR 2009: The Israeli Experimental Systems Conference,
ser. SYSTOR ’09. New York, NY, USA: ACM, 2009, pp. 10:1–10:9.
[5] M. Murugan and David.H.C.Du., “Rejuvenator: A static wear
leveling algorithm for nand flash memory with minimized overhead.”
Mass Storage Systems and Technologies (MSST), 2011.
[6] Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo., “Improving flash wearleveling
by proactively moving static data.” IEEE Transactions on
Computers, vol. 59, no. 1, pp. 53 – 65, 2009.
[7] M.-C. Yang, Y.-H. Chang, C.-W. Tsao, and P.-C. Huang., “New
ERA: new efficient reliability-aware wear leveling for endurance
enhancement of flash storage devices.” Design Automation Conference
(DAC), May 2013.
[8] Y.-J. Woo and J.-S. Kim., “Diversifying wear index for mlc nand
flash memory to extend the lifetime of ssds.” Embedded Software
(EMSOFT), pp. 1 – 10, 2013.
[9] L.-P. Chang, “A hybrid approach to nand-flash-based solid-state
disks,” pp. 1337–1349, 2010.
[10] L.-P. Chang and C.-D. Du, “Design and implementation of an
efficient wear-leveling algorithm for solid-state-disk microcontrollers.”
ACM Trans. Design Autom. Electr. Syst., vol. 15, 2009.
[11] UMassTraceRepository, “Oltp application i/o,”
http://traces.cs.umass.edu/index.php/Storage/Storage.
[12] N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares,
F. Trivedi, E. Goodness, and L. Nevill, “Bit error rate in nand flash
memories.” Reliability Physics Symposium(IRPS), pp. 9 – 19, 2008.
[13] “128gb, 256gb, 512gb async/sync enterprise nand features,”
http://www.micron.com/parts/nand-flash/enterprise-nand/.
[14] SpecTek, 64 Gb TLC NAND Flash Features FNNB74A.
[15] Micron, 128Gb MLC NAND Flash Memory MT29F128G08CBEBB.

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