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研究生: 賴冠甫
Guan-Fu Lai
論文名稱: 奈米級橫向溝渠式穿隧場效電晶體之設計
Design of Nanoscale Lateral Trench-Type Tunneling Field-Effect Transistor
指導教授: 莊敏宏
Miin-Horng Juang
口試委員: 徐世祥
Shih-Hsiang Hsu
張勝良
Sheng-Lyang Jang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 英文
論文頁數: 130
中文關鍵詞: 穿隧式場效電晶體奈米級
外文關鍵詞: Tunneling FET, TFET
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  • 隨著電子產業的進步,傳統型金氧半電晶體在尺寸微縮化之後面臨一些可靠度問題,例如短通道效應、熱載子效應、汲極引起位障降低效應、閘極引起汲極漏電流效應。然而,穿隧型場效電晶體的工作原理與傳統金氧半元件有所不同,因為它是靠源極與通道間的能帶穿隧效應產生電流,而不是靠源極電子跨越能障產生電流,所以它可以提供較小的短通道效應、小的熱載子效應以及降低汲極引起位障降低。較可以解決因微型化而造成的可靠度問題。
    儘管穿隧型場效電晶體能改善傳統金氧半電晶體的缺點並且成為低功耗系統應用的潛力元件,但還是面臨一些需要被解決的問題,例如過低的導通電流,此論文目的就是透過元件結構的改變以及相關參數模擬分析來實踐獲得高性能的穿透式場效電晶體。在本篇研究透過模擬設計了新型態的溝渠式穿隧場效電晶體,若將其與一百奈米的平面式穿隧場效電晶體比較,新設計的結構因為溝渠的轉角效應漏電流相當的低,然而導通電流卻跟平面式的差距很小,因此這新結構的元件有希望應用於奈米積體電路。


    In the progress of the electronics industry, the scaled down of the conventional MOSFET device will emerge some reliability problems, such as short-channel effect, hot-carrier effect, and gate-induced-drain leakage (GIDL). Tunneling Field Effect transistors (TFETs) are semiconductor devices that carry current via inter-band source-to- channel tunneling rather than by carrier transport over the source barrier. In other words, TFET has the immunity from these problems in high scaling fabrication due to its operation mechanism is different from the MOSFET device.
    Although tunneling-field effect transistors (TFETs) can improve disadvantages of conventional MOSTFT and become very promising candidates for future low power applications, some problems of TFET are still needed to be resolved such as very low on-state current compared to the conventional MOSFETs. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. In this study, there is a newly designed TFET structure called“the trench TFET with n-pocket”. For nanoscale devices, as compared to the planar TFET, the trench TFET with n-pocket can lead to a much smaller off-state current but comparable on-state current, due to the corner effect. Consequently, the trench TFET with n-pocket can be promising for nanoscale integrated-circuit devices.

    Abstract (Chinese)…………………………………………………….....II Abstract…………………………………………………………………IV Acknowledgement (Chinese)……………………………………..…….VI Contents………………………………………………………..………VII Table Lists………………………………………………………………IX Figure Captions…………………………………………………………..X Chapter 1 Introduction……………………………………………………1 1-1 Conventional MOSFET device……………………………………2 1-1-1 Short-channel effects………………………………………..2 1-1-2 Drain-induced barrier lowering (DIBL)……………………..3 1-1-3 Hot-carrier effect…………………………………………….4 1-1-4 Gate-induced-drain leakage (GIDL)………………………...4 1-2 TFET background………………………………..………………..5 1-2-1 Conventional TFET device operating principle…………….5 1-2-2 Other TFET structure designs……………………………….6 1-3 Motivation…………………………………………………………9 1-4 Thesis organization………………………………………..……...10 Chapter 2 Device Scheme……………………………………………….18 2-1 The fabrication of the SOI trench MOSFET structure...................19 2-2 The fabrication of the SOI trench TFET with n-pocket structure..31 Chapter 3 Results and discussion……………………………………….45 3-1 The planar TFET and the trench TFET…………….…….............45 3-2 The trench TFET and the trench TFET with n-pocket...................80 Chapter 4 Conclusions…………………………………………………107 Reference………………………………………………………..……..108

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