研究生: |
邱顯強 Shian-Chiang Chiou |
---|---|
論文名稱: |
移動物偵測之影像硬體架構 Image Hardware Structure of Motion Detection System |
指導教授: |
許孟超
Mon-Chau Shie |
口試委員: |
阮聖彰
Shanq-Jang Ruan 鄭瑞光 Ray-Guang Cheng |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 中文 |
論文頁數: | 73 |
中文關鍵詞: | FPGA 、影像處理 、電腦視覺技術 、智慧型交通系統 、移動物偵測 、智慧型視訊監控系統 、CMOS Camera 、SOPC |
外文關鍵詞: | Image Processing, Motion Detection, Computer Visualization Technology, Intelligent Traffic Control System, Intelligent Video Surveillance and Monitoring, FPGA, SOPC, CMOS Camera |
相關次數: | 點閱:275 下載:6 |
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移動物偵測是智慧型視訊監控系統、智慧型交通系統等基於電腦視覺技術內的一個極為重要步驟,目的都在於能夠更準確、快速的偵測到移動物件,其後續的工作如:移動物的追蹤、辨認等程序都高度依賴移動物偵測的準確與否,所以移動物偵測的正確性甚至足以決定整個系統的可靠度與精確性,是評估一個監控系統好壞的決定性因素。
實現移動物偵測,首先用背景相減法取得前景影像,利用5×5的遮罩,經過形態學的侵蝕運算與膨脹運算,分別來消除雜訊、連接紋理以及加強前景影像,然後利用連通元件將移動物框選,完成移動物偵測。而移動物偵測系統上牽涉到許多影像處理的技術,包含二值化、膨脹、侵蝕和連通等大量資料運算,耗費相當多的處理時間。
本論文主要為設計影像處理等各個硬體模組,實現於DE2 FPGA實驗板上。以Altera NIOS II嵌入式軟核心處理器及SOPC平台為開發環境,結合外接式的CMOS Camera當作影像來源,系統使用像素設定為320×240,透過VGA輸出將移動物偵測的畫面顯示在Monitor上,降低整體系統成本。最主要的設計重點,為了將影像作即時處理,改良形態學的硬體演算法,而本論文所提出的形態學硬體演算,處理一張320×240的影像只需花費約76,800個Clocks,比形態學硬體演算法-1[1]快約34倍,比形態學硬體演算法-2[2]執行快約6倍,有效的大幅提升處理速度。
Motion detection is a very important part of Intelligent Video Surveillance and Monitoring and Intelligent Traffic Control Systems based on the computer visualization technology. Its purpose is to detect moving objects more quickly and accurately and follow up tasks, such as: tracking and identifying moving objects which is reliant on the high accuracy of the motion detection. Therefore, the precision of the motion detection results can decide the system’s reliability and accuracy, which makes it a deciding factor for evaluating the surveillance systems.
To detect a moving object, I use background subtraction to retrieve the foreground image, by using a 5*5 mask, through morphology operations: erosion operation which reduces noise and dilation operation to reduce image discontinuity and enhance foreground image. Finally, by using the connected component and the moving object could be framed and tracked thus completing the motion detection. Overall, many image processing techniques were used in the system including: image binarization, dilation, erosion, and connecting component. These techniques require great processing data and extended amount of processing times.
This thesis is mainly dedicated to designing image processing hardware modules on the experimental board of DE2 FPGA. Using Altera NIOS II embedded processor and SOPC platform as the developing environment along with an external CMOS Camera as the video source, the motion detection video frames are displayed on a monitor. This lowers the overall system cost and processes the images in real-time.
The morphology hardware architecture in our paper spends almost 76,800 clocks to process a 320×240 picture. It’s faster than Harware Algorithm-1 by 34 times and faster than Harware Algorithm-2 by 6 times. Because of above description, we conclude that our architecture effectively improves speed.
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