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研究生: LUCKY KUMAR PRADHAN
LUCKY KUMAR PRADHAN
論文名稱: 適用於空間受限應用的超小面積低溫靈敏度片上 ALL-MOS 張弛振盪器
Ultra-Small Area Low Temperature Sensitivity On-Chip ALL-MOS Relaxation Oscillator for Space-Constrained Applications
指導教授: 陳伯奇
Po-Ki Chen
口試委員: 陳信樹
Hsin-Shu Chen
鍾勇輝
Yung-Hui Chung
盧志文
Chih-Wen Lu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 英文
論文頁數: 96
中文關鍵詞: 張弛振盪器低溫靈敏度絕對溫度互補MOS 電容器Python自動優化
外文關鍵詞: ALL-MOS, MOS Virtual Resistors, MOS Capacitors, Automatic Optimization
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在本論文中,我們提出了一種具有低溫敏感性的低功耗、超小面積片上張弛振盪器的開發設計。該電路受益於新引入的自動優化流程,可有效調整 MOSFET 參數。為了克服大面積消耗無源元件的挑戰,我們用 MOS 虛擬電阻器和 MOS 電容器取代電阻器和電容器,從而使設計變得更加緊湊。為了補償振盪器固有的 PTAT 行為,我們採用了通過充當虛擬電阻器的 MOSFET 實現的 CTAT 偏置電路。在 TSRI(台灣半導體研究所)的協助下,所提出的設計已在 TSMC 0.18μm 標準 CMOS 工藝中成功製造。該張弛振盪器在-25℃至+125℃的溫度範圍內實現了11.39MHz的穩定頻率工作,溫度係數為28.17 ppm/℃。在 1.3V 電源電壓下,其功耗為 243.1μW。值得注意的是,這種創新電路設計佔用的超小核心芯片面積僅為0.009mm2。通過自動優化,我們通過一系列Python程序減少了MOSFET調整大小問題的大量時間消耗。通過這項工作,我們顯著推進了振盪器設計,以緊湊的外形尺寸提供了更高的性能、溫度穩定性和效率,非常適合空間受限的應用。


In this thesis, we present a developed design of a low-power, ultra-small area on-chip relaxation oscillator with low-temperature sensitivity. The circuit benefits from a newly introduced automatic optimization process that effectively resizes MOSFET parameters. To overcome the challenge of large area-consuming passive components, we replace resistors and capacitors with MOS virtual resistors and MOS capacitors, resulting in a significantly more compact design. To compensate for the inherent PTAT behavior of the oscillator, we employ a CTAT biasing circuit implemented through a MOSFET which act as a virtual resistor. The proposed design is successfully fabricated in a TSMC 0.18μm standard CMOS process with the assistance of TSRI (Taiwan Semiconductor Research Institute). This relaxation oscillator achieves a stable frequency operation of 11.39MHz over the temperature range of -25℃ to +125℃ with the temperature coefficient of 28.17 ppm/℃. It has a power consumption of 243.1µW at a 1.3V supply voltage. Notably, this innovative circuit design occupies an ultra-small core chip area of just 0.009mm2. With automatic optimization, we reduce the large time consumption for MOSFET resizing issue with a series of python programs. Through this work, we significantly advance oscillator design, offering improved performance, temperature stability, and efficiency in a compact form factor ideal for space-constrained applications.

Table of Contents ACKNOWLEDGEMENTS i ABSTRACT iii 摘要 ii Table of Contents ii List of Figures v List of Tables viii List of Abbreviations ix CHAPTER 1 INTRODUCTION 1 1.1 Background 1 1.2 Motivation 2 1.2 Contribution 4 1.3 Organization 4 CHAPTER 2 LITERATURE REVIEW 6 Result Comparison for these Papers 9 CHAPTER 3 RESISTOR–LESS AND CAPACITOR-LESS RELAXATION OSCILLATOR CIRCUIT DESIGN 11 3.1 Design Flow 11 3.2 Circuit Design and Analysis 15 3.3 Main Components of Resister-less and Capacitor-less Relaxation Oscillator 17 3.3.1 Core Circuit 17 3.3.2 Complete Bias Circuit 26 3.3.3 CTAT Current Reference Circuit 28 3.3.4 MOS-Capacitor 28 3.3.5 SR-Latch 30 3.4 Automatic Optimization 31 3.4.1 Algorithm Descriptions: 32 3.4.2. Step by Step Process of Automatic Optimization 35 3.4.3. Discussions: 45 CHAPTER 4 LAYOUT IMPLEMENTATION 46 4.1 Mismatch 46 4.1.1 Common Centroid Layout 47 4.2 Designed ROSC Layout 48 4.2.1 Layout of CTAT Current Reference Circuit 49 4.2.2 Layout of Main Biasing and Oscillator Circuit 51 4.2.3 MOS-Capacitor Layout 55 4.2.4 Top-Cell layout 57 4.3 DRC and LVS Results 60 4.3.1 DRC Result 60 4.3.2 LVS Result 61 CHAPTER 5 SIMULATION AND MEASUREMENT RESULTS 63 5.1 Simulation Results 63 5.1.1 Pre-Layout Simulation 64 5.1.2 Post-Layout Simulation 72 5.2 Measurement Results 75 5.2.1 Measurement Method 75 5.2.2 Measurement Procedure 75 5.2.3 Measurement Results 84 5.3 Discussion 86 CHAPTER 6 CONCLUSION AND RECOMMENDATIONS 88 6.1 Conclusion 88 5.2 Future Work Recommendations 89 CHAPTER 7 BIBLIOGRAPHY 90

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