本論文提出了應用於5G 行動通訊系統中的可配置低密度奇偶檢查碼(LDPC)解碼器超大型積體電路(VLSI)設計與實作，在硬體架構上以降低面積為目標。在新架構上藉由設計改變檢查矩陣的位移量以減少循環移位器電路，並利用降低硬體平行度方法減少運算元的數量，達到以時間換取空間的效果。本論文也對因解碼方式採用TDMP方式產生的資料相依性造成硬體運算元空閒時間的問題提出檢查矩陣排程方法以及提供算式計算空閒時間的產生，此方法可以針對使用TDMP的不同電路架構進行排程。在檢查矩陣較大的情況下，此方法雖然不能找到所有可能性的最佳解，但能夠在有限的時間內找出較原本優秀的方法。經過實驗，在5G Base Graph 2 (BG2)中運用此排程方法，在不增加任何硬體資源的情況下，根據不同的架構能將吞吐量平均提升20%。
本篇論文使用TSMC 90nm CMOS製程技術進行實作，晶片核心面積為9.62mm2 ，晶片總面積為13.34mm2 ，功耗為607.73mW。在工作頻率為200MHz，最大解碼數為8次下，最高吞吐量可達356Mbps，若使用提前決斷電路在訊雜比高情況下，最高吞吐量可以達到1.424Gbps。

This thesis proposes the design and implementation of configurable low-density parity check decoder for 5G mobile communication sysyems. The purpose of design is reducing chip area. The novel decoder architecture reduces a cyclic shift circuit and number of processing units by designing the new parity check matrix and reducing the hardware parallelism. This thesis also proposes a method for the hardware implement issue introduced by TDMP due to data dependency characteristic. The method can be scheduled for the different hardware architecture which used TDMP algorithm. In the case of large parity check matrix, this method can not find the best solution of all possibilities, but it can find the better solution than original in limited time. In our experiment, average throughput can increase 20% by using the method without extra hardware resources in 5G Base Graph 2(BG2).
The decoder is implemented using a TSMC 90nm CMOS technology. The core area is 9.62mm2 and the total chip area is 13.34mm2 and power consumption is 607.73mW and the maximum clock frequency is 200MHz and the maximum iteration number is 8. The throughput can reach 356Mbps at the maximum clock frequency and the maximum iteration number. The highest throughput can reach 1.424Gbps at high Signal-to-noise ratio with early termination circuit.

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