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研究生: 戴伯叡
Bo-Rui Dai
論文名稱: 具雙八字形電感駐波振盪器和新型兩圈八字電感的互補式壓控震盪器與低雜訊放大器
Standing-Wave Oscillator with a Double-8-shaped Inductor and Complementary VCO and LNA with a New two-turn Eight inductor
指導教授: 張勝良
Sheng-Lyang Jang
口試委員: 張勝良
Sheng-Lyang Jang
莊敏宏
Miin-Horng Juang
張珈瑋
Chia-Wei Chang
徐茂修
Mao-Hsiu Hsu
學位類別: 碩士
Master
系所名稱: 電資學院 - 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年: 2023
畢業學年度: 112
語文別: 英文
論文頁數: 117
中文關鍵詞: 駐波震盪器八字電感電感等校模擬低雜訊放大器
外文關鍵詞: Standing-Wave Oscillator, 8-shaped Inductor, 8-shaped Inductor Circuit modle, Low-Noise Amplifier
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現今在射頻(RF)電路中,壓控頻率振盪器(VCO)為一個關鍵元件,它在許多應用中扮演著關鍵性的角色。其輸出頻率可以通過調整輸入電壓的大小而改變。VCO常用於產生可變頻率的信號,這對於調變、頻率合成和時序控制等應用非常重要。所以本篇論文分別呈現了三篇 VCO與一篇LNA的設計。
首先設計了一個9.90 GHz的駐波振盪器(SWO)。SWO使用一圈雙8字形電感作為波傳輸的傳輸線,並使用三對互補的MOS反相器作為負電阻產生器。這三個反相器放置在電感的內部,以節省晶片面積。製造完成所佔用面積為0.947×0.848平方毫米。在1.2伏特的電源電壓和4.3毫瓦的功耗下,SWO的FOM為-188.59 dBc/Hz。由於使用了8字形電感,SWO具有耦合噪聲壓制的特性。
第二顆晶片為改良第一顆是使用了第一部分作為改良利用multi path的方式改良電感以降低電流於電感的集膚效應。當電源電壓給1.65V時MOSFET會開啟使電感呈短路狀態,此時電源電壓在1.2V時,頻率7.9GHz,功耗為 8.7 mW,而相位雜訊在 1 MHz 時為 -117.5 dBc/Hz、FOM 值為 -184.3 dBc/Hz。而當開關電壓0V時MOSFET會關閉使電感呈斷路狀態,此時電源電壓在0.8V時,頻率3.8GHz,功耗為 3.1 mW,相位雜訊在 1 MHz 時為 -113.8 dBc/Hz、FOM 值為 -181.5 dBc/Hz。
第三與四顆是利用0.18μm CMOS工藝下製造的3.58 GHz LC-tank電壓調控振盪器(VCO)。這個互補式VCO使用一個兩圈的8字形電感作為諧振電感,與可變電容並聯用於頻率調節。由於使用了8字形電感,VCO具有耦合噪聲抑制的特性。NMOS交叉耦合對使用尾電感,而pMOS交叉耦合對則使用源極衰減電感來降低噪聲。這三個電感被放置在同一區域內,以減小晶片的尺寸
最後一部分為提出了一種低雜訊放大器(LNA),採用了雙圈8字形電感進行輸入匹配。8字形電感器使用了兩個串聯的雙圈八邊形電感。為了減少磁場耦合雜訊,採用了完全對稱的雙圈交叉電感。在2.2 GHz頻率下,在0.18 μm的CMOS工藝下,該LNA表現出11.62 dB的增益,3.79 dB的噪聲係數,-12.56 dBm的P-1dB,以及-9.33 dBm的輸入三階截止點(IIP3)用於低頻段。所設計的LNA是一個在4.8 GHz高頻段運行的雙頻段並行LNA。與寬頻LNA相比,多頻段LNA提供了阻帶抑制和耦合抑制。


In today's RF (Radio Frequency) circuits, Voltage-Controlled Oscillators (VCOs) play a crucial role as a key component. They alter their output frequency by adjusting the input voltage. VCOs are commonly used for generating signals with variable frequencies, which is essential for applications such as modulation, frequency synthesis, and timing control. Therefore, this paper presents the designs of three VCOs and one Low-Noise Amplifier (LNA).

First, a 9.90 GHz LC-tank Voltage-Controlled Oscillator (VCO) is designed. This VCO utilizes a single-loop, dual 8-shaped inductor as a transmission line for wave propagation and employs three pairs of complementary MOS inverters as a negative resistance generator. These three inverters are placed inside the inductor to save the chip area. The manufactured VCO occupies an area of 0.947×0.848 mm2, including the buffer area. With a supply voltage of 1.2 volts and a power consumption of 4.3 milliwatts, the Figure of Merit (FOM) for the VCO is -188.59 dBc/Hz. Due to the use of 8-shaped inductors, this VCO exhibits noise coupling suppression characteristics.

The second chip is an improved version of the first one and employs multipath techniques to mitigate skin effect-induced current in the inductor. When the supply voltage is set to 1.65V, the MOSFET switches on, short-circuiting the inductor. At this point, with a 1.2V supply voltage, the frequency is 7.9 GHz, power consumption is 8.7 mW, and the phase noise at 1 MHz is -117.5 dBc/Hz, with an FOM of -184.3 dBc/Hz. When the switch voltage is 0V, the MOSFET turns off, causing the inductor to be open-circuited. In this state, with a 0.8V supply voltage, the frequency is 3.8 GHz, power consumption is 3.1 mW, and the phase noise at 1 MHz is -113.8 dBc/Hz, with an FOM of -181.5 dBc/Hz.

The third and fourth chips are 3.58 GHz LC-tank Voltage-Controlled Oscillators (VCOs) fabricated using a 0.18μm CMOS process. These complementary VCOs employ a two-loop 8-shaped inductor as a resonant inductor, along with variable capacitors for frequency tuning. Due to the use of 8-shaped inductors, these VCOs also exhibit noise coupling suppression characteristics. NMOS cross-coupling utilizes tail inductors, while pMOS cross-coupling utilizes source degeneration inductors to reduce noise. All three inductors are placed in the same region to minimize chip size.

In the final part, the fifth chip presents a Low-Noise Amplifier (LNA) that uses dual-loop 8-shaped inductors for input matching. Two serially connected dual-loop octagonal inductors are used, and fully symmetric dual-loop twisted inductors are employed to minimize magnetic field-coupled noise. At a frequency of 2.2 GHz and using a 0.18 μm CMOS process, this LNA exhibits a gain of 11.62 dB, a noise figure of 3.79 dB, a P-1dB of -12.56 dBm, and an Input Third-Order Intercept Point (IIP3) of -9.33 dBm for the low-frequency band. The designed LNA operates as a dual-band concurrent LNA in the high-frequency band at 4.8 GHz. Compared to a wideband LNA, the multi-band LNA provides band rejection and coupling suppression.

摘要 2 Abstract I 致謝 III Table of Contents IV List of Figures VIII List of Tables XI Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Organization 4 Chapter 2 Fundamental Principles and Design Factors for Voltage Controlled Oscillators 6 2.1 Introduction 6 2.2 The Oscillators Theory 8 2.2.1 Feedback Oscillators (Two port) 8 2.2.2 Negative Resistance and Resonator (One port) 10 2.3 Category of Oscillators 11 2.3.1 Ring Oscillator 11 2.3.2 LC-Tank Oscillator 16 2.4 Design Concepts of Voltage-Controlled Oscillator 20 2.4.1 Parameters of a Voltage-Controlled Oscillator 22 2.4.2 Phase Noise 24 2.4.3 Quality Factor 28 Chapter 3 Design of Low-Noise amplifier 30 3.1 Introduction 30 3.2 Basic Architecture of Low Noise Amplifier 32 3.2.1 Common Source Architecture 22 3.2.2 Feedback Circuit Architecture 26 Chapter 4 Area-Efficient Standing-Wave Oscillator with a Double-8-shaped Inductor 41 4.1 Introduction 41 4.2 Circuit Design 44 4.3 Measurement and Discussion 46 Chapter 5 Dual-Band Standing Wave Oscillator with MOSFET Switch 50 5.1 Introduction 50 5.2 Circuit Design 52 5.3 Measurement and Discussion 57 Chapter 6 Complementary VCO with a New 2-turn 8-shaped Inductor 72 6.1 Introduction 72 6.2 Circuit Design 73 6.3 Measurement and Discussion 75 6.4 Circuit Design 81 6.5 Measurement and Discussion 84 Chapter 7 CMOS Low Noise Amplifier Using Twisted Inductor 89 7.1 Introduction 89 7.2 Circuit Design 92 7.3 Measure and Discussion 97 7.4 Improve Design 102 Chapter 8 Conclusions 106 References 108

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