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研究生: 蘇陳銘祥
Ming-Hsiang Suchen
論文名稱: 注入鎖定除頻器與八相位壓控振盪器之設計
Design of Injection-Locked Frequency Divider and Eght-Phase Voltage-Controlled-Oscillator
指導教授: 張勝良
Sheng-Lyang Jang
口試委員: 徐敬文
Ching-Wen Hsue
黃進芳
Jhin-Fang Huang
莊昀學
Yun-Hsueh Chuang
鄧恆發
Heng-Fa Teng
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 100
中文關鍵詞: 除頻器壓控振盪器變壓器八相位
外文關鍵詞: drivider, 3D transformer, eight phase
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  • 本論文題材專注於壓控振盪器和注入鎖定除頻器。第一部份討論以可變電容與偏壓的組合方式,來改善LC壓控振盪器的可調變頻率曲線的非線性缺點,然後再描述注入鎖定除頻器的原理。
    第二部份提出互補式考畢子注入鎖定除頻器,使用3-D螺旋變壓器設計,此電路針對使用3-D電感來縮減晶片面積,而除二注入鎖定除頻器,則是利用nMOS連接到壓控振盪器的差動輸出端,達到除頻效果。在電源1.8V量測到頻率可調範圍從4.23GHz到4.8GHz,注入功率大小為0dBm,Vtune=0.9V和VDD=1.5V時鎖定範圍高達2.4GHz(26.9%),從7.7GHz到10.1GHz,功率消耗3.9mW,晶片面積為0.548 x 0.656 mm2.
    第三部份提出低雜訊八相位壓控振盪器,此低雜訊壓控振盪器,皆採用台積電所提供之零點一八微米互補式金氧半製程所製造,此電路透過兩組nMOS耦合四相位壓控振盪器,鎖定壓控振盪器的二倍頻率,達到八相位的效果。振盪器工作在5.1 GHz到5.5 GHz,7.6%的可調範圍,輸出之相位雜訊在距離5.1GHz載波頻率1MHz處所量測之結果可達-115.4dBc/Hz,在VDD=1時功率消耗7.43mW。


    This thesis is devoted to the subject of CMOS voltage controlled oscillators (VCO) and Injection-locked frequency divider (ILFD).
    The first part proposes the method to improve the nonlinear drawbacks of conventional LC-Voltage-controlled oscillators by a new varactor structure, and then describes basic theories of injection-locked frequency divider
    The second part proposes complementary Colpitts injection-locked frequency divider (ILFD) employing a 3-dimensional (3-D) helical transformer. The aim of using the 3-D transformer is to reduce chip size. The divide-by-2 LC-tank ILFD is implemented by adding an injection nMOS between the differential outputs of the VCO. The measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 4.24 GHz to 4.8 GHz. At the incident power of 0 dBm, vtune = 0.9 V, and VDD = 1.5 V, the locking range is about 2.4 GHz (26.9%), from the incident frequency 7.7 GHz to 10.1 GHz. The core power consumption is 3.9 mW. The die area is 0.548 x 0.656 mm2.
    The third part presents an eight-phase low phase noise CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and adopts two quadrature cross-coupled nMOS-core VCOs injection-locked through the second-harmonic. The VCO operates from 5.1 GHz to 5.5 GHz with 7.6 % tuning range. The measured phase noise at 1-MHz offset from 5.1 GHz is about -115.4dBc/Hz. The power consumption of the VCO core is 7.43 mW at the supply voltage of 1V.

    中文摘要 I ABSTRACT II 誌謝 III CONTENTS IV LIST OF FIGURES VI LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 ANALYSIS OF OSCILLATORS 5 2.1 THE OSCILLATOR THEORY 5 2.1.1 Negative Resistance (NR) 6 2.1.2 Positive Feedback (PFB) 8 2.2 ALL TYPES OF OSCILLATORS 10 2.2.1 Ring Oscillator 11 2.2.2 LC-Tank Oscillator 14 2.3 VOLTAGE-CONTROLLED OSCILLATOR 17 2.4 THE PARAMETERS OF VCOS 18 2.4.1 Center Frequency 18 2.4.2 Tuning Range 19 2.4.3 Tuning Linearity 20 2.4.4 Output Amplitude 20 2.4.5 Power Dissipation 21 2.4.6 Supply and Common-Mode Rejection 21 2.4.7 Output Signal Purity 21 2.5 PHASE NOISE 22 2.5.1 Definition of Phase Noise 22 2.5.2 Existing Models of Phase Noise 24 2.5.2.1 Time-invariant phase noise model 24 2.5.3 Noise Sources 27 2.5.3.1 Thermal noise 27 2.5.3.2 Flicker noise 30 2.5.4 Phase Noise in Wireless Communication 31 2.5.5 Previous Models of Phase Noise 34 2.6 ON-CHIP INDUCTOR RESEARCH 35 2.6.1 Inductor Categories 35 2.6.2 Loss Mechanisms of Inductor 37 2.6.2.1 Metal Loss 37 2.6.2.2 Substrate Loss 38 2.6.2.3 Definitions of Inductor Parameters 39 2.7 VARACTOR 40 2.7.1 P-N Junction Varactor 40 2.7.2 MOS Varactor 41 2.7.2.1 Accumulation-mode MOS varactor 43 2.7.2.2 Inversion-mode MOS varactor 44 CHAPTER 3 THEORY OF ILFD 46 3.1 INTRODUCTION 46 3.2 CLASSIFICATION OF ANALOG FREQUENCY DIVIDERS 47 3.3 BASIC CONCEPT FOR ILFD 48 3.3.1 Injection Locking 48 3.3.2 Model of ILFD 50 3.3.2.1 General Case 50 3.3.2.2 Special Case 51 3.3.3 Noise in ILOs 53 3.4 CLASSIFICATION OF ILFDS 55 3.5 BASIC TOPOLOGY OF DIVIDE-BY-2 ILFD 57 CHAPTER 4 ILFD IMPLEMENTED WITH A 3-D TRANSFORMER 59 4.1 INTRODUCTION 59 4.2 CIRCUIT DESIGN 60 4.3 MEASUREMENT RESULTS 66 CHAPTER 5 AN EIGHT-PHASE VCO 71 5.1 INTRODUCTION 71 5.2 QUADRATURE VCO CIRCUIT DESIGN 72 5.3 EIGHT-PHASE VCO CIRCUIT DESIGN 74 5.4 MEASUREMENT RESULTS 78 CHAPTER 6 CONCLUSION 82 REFERENCES 84

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