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研究生： 林延簇
Yan-Cu Lin
論文名稱： 低功耗及低相位雜訊壓控振盪器與四相位壓控振盪器之設計
Design of Low Power Consumption and Low Phase Noise Voltage-Controlled Oscillator and Quadrature Voltage-Controlled Oscillator
指導教授： 徐敬文
Ching-Wen Hsue
張勝良
Sheng-Lyang Jang
口試委員: 黃進芳
Jhin-Fang Huang
馮武雄
Wu-Shiung Feng
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 136
中文關鍵詞： 原生金屬氧化物半導體 、變壓器 、低功耗 、相位雜訊 、壓控振盪器
外文關鍵詞： Low power consumption, Phase noise, Voltage controlled oscillator, Transformer, Native MOSFET
相關次數： 點閱：323  下載：5 
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    • 無線通訊系統在現代社會中快速的成長，其要求高速度以及極小誤差的情況下，PLL的特性將會是其要求的重點，PLL中包含相位頻率比較器、迴路濾波器、壓控振盪器、除頻器等，其中又以壓控振盪器為最重要的部分，要求在低功耗中有著低相位雜訊以及較寬工作範圍的特性，並由FoM定義其特性的好壞。
    首先，本論文提出一個超低供應電壓的壓控振盪器被實現在台積電矽鍺點一八製程。此電路是以近零導通電壓的原生金屬氧化物半導體當作負阻抗，並加上變壓器做為振盪源以及輸出振福的增加，並且利用自製變壓器節省電路面積。在電源電壓0.2V，在1MHz偏移頻率相位雜訊為-108.12 dBc/Hz其振盪頻率為978MHz，以及FOM數值為-170.6 dBc/Hz。總消耗功率為0.536毫瓦，其可調範圍約130MHz，從978至1108 MHz，當控制電壓從0V至2V，晶片面積為0.472×0.722mm2。
    其次，一個四相位壓控振盪器使用動態偏壓達到易起振並省電的效果且利用變容器耦合產生四相位並達到低相位雜訊，此電路由台積電點一八製程技術完成。在電源電壓1.1V以及調整電壓為0.7V時，在1MHz偏移頻率相位雜訊為-130.34 dBc/Hz其振盪頻率為2.03 GHz，以及FOM數值為-190.6 dBc/Hz。壓控振盪器之總消耗功率為3.9毫瓦，其可調範圍約422MHz，從1.978至2.4 GHz，晶片面積為0.528×1.168mm2。
    最後，提出一個低功耗及低相位雜訊的壓控振盪器被實現在台積電矽鍺點一八製程。此電路利用雜訊濾波器將二次諧波濾除以及自製電感來降低相位雜訊。在電源電壓1.2V時，在1MHz偏移頻率相位雜訊為-122.79 dBc/Hz其振盪頻率為2.479 GHz，以及FoM數值為-197 dBc/Hz。壓控振盪器之總消耗功率為0.24毫瓦，晶片面積為0.799×0.809mm2。

    Rapid growth has been achieved in wireless communication system nowadays. High efficiency and low error are required and phase locked loop (PLL), with the voltage controlled oscillator (VCO) and the divider circuit, plays an important role in the trend. The VCO requested with low phase-noise, low power consumption and wide tuning rage, and the performance of VCO can be examined by the Figure of Merit (FOM).
    First, this thesis features an ultra-low supply voltage VCO, which implemented in TSMC SiGe 0.18μm 3P6M CMOS process. The circuit not only uses a native MOSFET of near zero threshold voltage as negative transconductor, but also designs a transformer as resonator tank to increase the output swing. Chip area is also saved with the homemade transformer.. At the supply voltage of 0.2 V, the output phase noise of the VCO is -108.12 dBc/Hz at 1MHz offset frequency from the carrier frequency of 978MHz, and the figure of merit is -170.6 dBc/Hz. Total power consumption is 0.536mW. Tuning range is about 111MHz, from 978 to 1108MHz, while the control voltage was tuned from 0 V to 2 V. The die area is 0.472 × 0.722 mm2.
    Second, a quadrature voltage controlled oscillator (QVCO) achieves power-saving benefit and easier startup with dynamic biasing circuit. The phase noise of the proposed QVCO is also reduced by using varactor to generate quadrature phase. The chip was implemented using the TSMC 0.18μm CMOS 1P6M process. At the supply voltage of 1.1 V and tuning voltage at 0.7V, the output phase noise of the VCO is -130.34 dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.04GHz, and the figure of merit is -190.6 dBc/Hz. Total power consumption is 3.9mW. Tuning range is about 422MHz, from 1.978 to 2.4GHz, while the control voltage was tuned from 0 V to 2 V. The die area is 0.528 × 1.168 mm2.
    Finally, this thesis also proposes an oscillator which achieved low power consumption and low phase noise voltage controlled in TSMC SiGe 0.18μm 3P6M CMOS process. This circuit suppresses second harmonic with noise filter, while phase noise in the circuit is reduced with a homemade inductor. At the supply voltage of 1.2V, the output phase noise of the VCO is -122.79 dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.47GHz, and the figure of merit is -197 dBc/Hz. Total power consumption is 0.24mW. Tuning range is about 21MHz, from 2.479 to 2.5GHz, while the control voltage was tuned from 0 V to 2 V. The die area is 0.799 × 0.809 mm2.

    Table of Contents 中文摘要 I ABSTRACT III 誌謝 V TABLE OF CONTENTS VI LIST OF FIGURES VIII LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 OVERVIEW OF THE VOLTAGE-CONTROLLED OSCILLATORS 6 2.1 INTRODUCTION 6 2.2 BASIC THEORY OF OSCILLATORS 7 2.2.1 One-Port (Negative Resistance) View 8 2.2.2 Two-Port (Feedback) View 12 2.3 THE CLASSIFICATION OF OSCILLATORS 15 2.3.1 Ring Oscillator 15 2.3.2 LC-Tank Oscillator 17 2.3.3 Research of RLC Tank 22 2.3.4 Type of LC Oscillator 25 2.3.4.1 Single Transistor Oscillator 26 2.3.4.2 One-Port Oscillator (Negative-Gm Oscillator) 29 2.3.4.3 Cross-Coupled Oscillator 34 2.3.4.4 Complementary Cross-Couple Topology 36 2.3.4.5 Quadrature Voltage-Controlled Oscillator 38 CHAPTER 3 BASIC CONCEPT OF VOLTAGE-CONTROLLED OSCILLATOR DESIGN 43 3.1 DESIGN PARAMETER OF VOLTAGE-CONTROLLED OSCILLATOR 43 3.2 SIGNIFICANT ISSUE OF VOLTAGE-CONTROLLED OSCILLATOR 46 3.2.1 Definition of Phase Noise 46 3.2.2 Linear Time-Invariant (LTI) Phase Noise Model 48 3.2.3 Linear Time-Variant Phase Noise Model 52 3.2.4 Classification of Noise 54 3.2.4.1 Thermal Noise 55 3.2.4.2 Flicker Noise 57 3.2.4.3 Phase Noise in Communications 58 3.2.5 Quality Factor 60 3.3 ELEMENTS OF SEMICONDUCTOR PROCESS 61 3.3.1 Resistor 61 3.3.2 Inductor 62 3.3.3 Transformer 71 3.3.3.1 Planar Transformer 74 3.3.3.2 Stacked Transformer 75 3.3.4 Capacitor 76 3.3.5 Varactor 79 3.3.5.1 P-N Reverse Biased Diode 80 3.3.5.2 MOS Varactor 81 3.3.5.2.1 The Accumulation-Mode (A-mode) MOS Capacitor 84 3.3.5.2.2 The Inversion-Mode (I-mode) MOS Capacitor 85 CHAPTER 4 LOW SUPPLY VOLTAGE-CONTROLLED OSCILLATOR WITH TRANSFORMER FEEDBACK 86 4.1 INTRODUCTION 86 4.2 CIRCUIT DESIGN 87 4.3 MEASUREMENT RESULTS 88 CHAPTER 5 A QUADRATURE VCO USING NOVEL CLASS-C TECHNIQUE FOR LTE APPLICATION 95 5.1 INTRODUCTION 95 5.2 CIRCUIT DESIGN 96 5.3 MEASUREMENT RESULTS 97 CHAPTER 6 LOW-PHASE-NOISE VCO USING PMOS CROSS-COUPLED VCO STACKED ON A CLASS-C NMOS VCO 103 6.1 INTRODUCTION 103 6.2 CIRCUIT DESIGN 104 6.3 MEASUREMENT RESULTS 110 CHAPTER 7 CONCLUSION AND FUTURE WORK 114 7.1 CONCLUTIONS 114 7.2 FUTURE WORK 115 REFERENCES 116  List of Figures FIGURE 1.1.1 THE FRONT-END OF RF WIRELESS RECEIVER. [1] 2 FIGURE 1.1.2 THE PROBLEM OF IMAGE BAND SIGNAL IN DOWN-CONVERSION. [1] 2 FIGURE 1.1.3 HARTLEY IMAGE REJECT RECEIVER. 4 FIGURE 2.1.1 BLOCK DIAGRAMS OF PHASE-LOCKED LOOP. 6 FIGURE 2.2.1 ONE PORT VIEW OF OSCILLATORS. 8 FIGURE 2.2.2 RELATIONSHIP BETWEEN POLES LOCATION AND TRANSIENT RESPONSE [2] 9 FIGURE 2.2.3 ONE-PORT VIEW OF OSCILLATORS, (A) RLC TANK WITH NEGATIVE RESISTANCE.(B) POSSIBLE IMPLEMENTATION. 10 FIGURE 2.2.4 THE BASIC FEEDBACK CIRCUIT. 12 FIGURE 2.3.1 RING OSCILLATOR 16 FIGURE 2.3.2 REALIZATION A RING OSCILLATOR USING FULLY DIFFERENTIAL INVERTERS. 16 FIGURE 2.3.3 (A) IDEA LC TANK MODEL AND (B) ACTUAL LC TANK [5] 18 FIGURE 2.3.4 CONVERSION OF SERIES TO PARALLEL COMBINATION[5]. 19 FIGURE 2.3.5 LC RESONATOR IN REAL SITUATION AND ITS EQUIVALENT CIRCUIT [5]. 21 FIGURE 2.3.6 (A) MAGNITUDE AND (B) LC-TANK FREQUENCY WITH IMPEDANCE PHASE[5]. 21 FIGURE 2.3.7 PARALLEL OF RLC TANK CIRCUIT. 22 FIGURE 2.3.8 NOT-QUITE-PARALLEL RLC TANK CIRCUIT CONVERSIONS. 24 FIGURE 2.3.9 WAVEFORM OF AN LC RESONATOR WITH LOSSES COMPENSATED. 25 FIGURE 2.3.10 RESONATORS WITH FEEDBACK: (A) COLPITTS OSCILLATOR, (B) HARTLEY OSCILLATOR AND (C) NEGATIVE RESISTANCE OSCILLATOR. 26 FIGURE 2.3.11 (A) DIRECT FEEDBACK AND (B) FEEDBACK WITH IMPEDANCE TRANSFORMER. 26 FIGURE 2.3.12 (A) COLPITTS OSCILLATOR AND (B) HARTLEY OSCILLATOR. 27 FIGURE 2.3.13 CANCELED OF LOSS BY NEGATIVE RESISTANCE. 29 FIGURE 2.3.14 A RLC PARALLEL CIRCUIT. 30 FIGURE 2.3.15 (A) DECAYING IMPULSE RESPONSE OF A TANK (B) CANCEL LOSS IN RP BY ADD THE NEGATIVE RESISTANCE. [5]. 31 FIGURE 2.3.16 (A) SOURCE FOLLOWER WITH POSITIVE FEEDBACK TO CREATE NEGATIVE IMPEDANCE AND (B) EQUIVALENT CIRCUIT OF (A) THAT CALCULATE THE INPUT IMPEDANCE. 33 FIGURE 2.3.17 OSCILLATOR USE NEGATIVE INPUT RESISTANCE OF A SOURCE FOLLOWER WITH POSITIVE FEEDBACK [5]. 33 FIGURE 2.3.18 (A) CROSS-COUPLED DIFFERENTIAL TOPOLOGY AND (B) NEGATIVE RESISTANCE OF CROSS-COUPLED PAIR. 34 FIGURE 2.3.19 THE SIMPLE OSCILLATOR MODEL. 35 FIGURE 2.3.20 (A) COMPLEMENTARY CROSS-COUPLED DIFFERENTIAL TOPOLOGY, (B) WITH A TAIL CURRENT AT THE SOURCE OF NMOS PAIR, (C) WITH A TAIL CURRENT AT THE SOURCE OF PMOS PAIR AND (D) WITHOUT A TAIL CURRENT. 36 FIGURE 2.3.21 BLOCK DIAGRAM OF QUADRATURE OSCILLATOR. 38 FIGURE 2.3.22 THE QUADRATURE LC OSCILLATOR. 39 FIGURE 2.3.23 TUNING A QUADRATURE OSCILLATOR BY CHANGING THE COUPLING COEFFICIENT. 40 FIGURE 2.3.24 MULTI-PHASE COUPLED OSCILLATOR. 41 FIGURE 2.3.25 RING OSCILLATOR INCORPORATING COMMON-SOURCE STAGES WITH INDUCTIVE LOADS. 42 FIGURE 3.1.1 THE DEFINITION OF THE VCO GAIN WHICH IS DENOTED BY KVCO. 43 FIGURE 3.2.1 (A) IDEA SPECTRUM OF OSCILLATOR AND (B) ACTUAL SPECTRUM OF OSCILLATOR. 47 FIGURE 3.2.2 PHASE NOISE SPECTRUM. 48 FIGURE 3.2.3 A RLC TANK WITH NOISE SOURCE 48 FIGURE 3.2.4 NOISE INJECTED AT DIFFERENT TIME THAT RESULT IN (A) ONLY THE CHANGE OF AMPLITUDE OR (B) ONLY THE CHANGE OF EXCESS PHASE. 53 FIGURE 3.2.5 THERMAL NOISE OF RESISTOR. 55 FIGURE 3.2.6 THE THERMAL NOISE MODEL OF MOS TRANSISTOR. 56 FIGURE 3.2.7 THE POWER SPECTRUM OF THERMAL NOISE. 56 FIGURE 3.2.8 FLICKER NOISE OF A MOSFET 57 FIGURE 3.2.9 SPECTRUM OF FLICKER NOISE. 58 FIGURE 3.2.10 DOWN CONVERSION OF FREQUENCY WITH IDEAL CASE. 59 FIGURE 3.2.11 DOWN CONVERSION USING AN LO SIGNAL WITH PHASE NOISE. [23] 59 FIGURE 3.2.12 COMMON DEFINITIONS OF Q. 61 FIGURE 3.3.1 A BENDED SHEET RESISTOR. 62 FIGURE 3.3.2 PLANAR SPIRAL INDUCTOR. 63 FIGURE 3.3.3 SIMPLIFIED LUMPED-ELEMENT MODEL OF THE MONOLITHIC INDUCTOR. 63 FIGURE 3.3.4 GENERATE PLANAR INDUCTOR OF SUBSTRATE CURRENT. 64 FIGURE 3.3.5 GENERATION OF EDDY CURRENT IN PLANAR INDUCTOR. 65 FIGURE 3.3.6 ONE-PORT LUMPED-ELEMENT MODEL OF THE MONOLITHIC INDUCTOR. 66 FIGURE 3.3.7 ONE-PORT LUMPED-ELEMENT MODEL OF THE MONOLITHIC INDUCTOR. 68 FIGURE 3.3.8 THE VARIATION OF THE INDUCTANCE WHILE THE CONDUCTIVE SUBSTRATE IS EMPLOYED. 70 FIGURE 3.3.9 MONOLITHIC TRANSFORMER: (A) PHYSICAL LAYOUT. (B) SCHEMATIC SYMBOL. 72 FIGURE 3.3.10 FIRST-PASS LOSSLESS TRANSFORMER MODEL. 73 FIGURE 3.3.11 THE PLANAR TRANSFORMER STRUCTURES: (A) TAPPED, (B) PARALLEL, (C) INTERTWINED, AND (D) SYMMETRIC. 74 FIGURE 3.3.12 STACKED TRANSFORMER: (A) STRUCTURE AND (B) CIRCUIT MODEL. 75 FIGURE 3.3.13 SYMMETRIC STACKED INVERTING TRANSFORMER: (A) STRUCTURE, (B) TOP VIEW, AND (C) CIRCUIT. 76 FIGURE 3.3.14 PARALLEL PLATE CAPACITOR 77 FIGURE 3.3.15 CROSS SECTION OF A WOVEN CAPACITOR. 78 FIGURE 3.3.16 TOP VIEW OF A WOVEN CAPACITOR. 78 FIGURE 3.3.17 SYMBOL OF THE P-N VARACTOR AND ITS SIMPLIFIED MODEL. 80 FIGURE 3.3.18 TYPICAL STRUCTURES OF P-N REVERSE BIAS DIODE. 81 FIGURE 3.3.19 THE NMOS DEVICE IN THE (A) ACCUMULATION REGION, (B) DEPLETION REGION AND (C) INVERSION REGION. 82 FIGURE 3.3.20 (A) CROSS-SECTION VIEW AND (B) TUNING CHARACTERISTICS FOR THE MOS CAPACITOR WITH B CONNECTED TO D AND S. 83 FIGURE 3.3.21 (A) CROSS-SECTION VIEW AND (B) TUNING CHARACTERISTICS FOR THE ACCUMULATION-MODE MOS CAPACITOR. 84 FIGURE 3.3.22 (A) CROSS-SECTION VIEW AND (B) TUNING CHARACTERISTICS FOR THE INVERSION-MODE MOS CAPACITOR. 85 FIGURE 4.2.1 SCHEMATIC OF PROPOSED VCO WITH NATIVE MOS. 87 FIGURE 4.2.2 DEVICE CROSS-SECTIONAL VIEW OF THE MOSFETS IN TWIN-WELL CMOS TECHNOLOGY. 88 FIGURE 4.2.3 TRANSFER I-V CHARACTERISTICS OF CONVENTIONAL AND NATIVE MOSFETS. VDD=0.1V. W/L=0.25/0.3UM. 88 FIGURE 4.3.1 DIE PHOTOGRAPH. 89 FIGURE 4.3.2 MEASURED FREQUENCY TUNING RANGE AND PHASE NOISE OF THE PROPOSED VCO CIRCUIT. 89 FIGURE 4.3.3 MEASURED OUTPUT SPECTRUM OF THE PROPOSED VCO. 90 FIGURE 4.3.4 TRANSFORMER EM SIMULATION WITH ADS. 91 FIGURE 4.3.5 TRANSFORMER LD WITH ADS SIMULATION RESULT. 91 FIGURE 4.3.6 EQUAL SERIES RESISTANCE ABOUT LD WITH ADS SIMULATION RESULT. 92 FIGURE 4.3.7 TRANSFORMER LS WITH ADS SIMULATION RESULT. 92 FIGURE 4.3.8 EQUAL SERIES RESISTANCE ABOUT LD WITH ADS SIMULATION RESULT. 92 FIGURE 4.3.9 MUTUAL INDUCTANCE BETWEEN LD1 AND LD2. 93 FIGURE 4.3.10 MUTUAL INDUCTANCE BETWEEN LS1 AND LS2. 93 FIGURE 4.3. 11 MUTUAL INDUCTANCE BETWEEN LD1 AND LS1. 93 FIGURE 4.3.12 MUTUAL INDUCTANCE BETWEEN LD1 AND LS2. 94 FIGURE 5.2.1 SCHEMATIC OF CONVENTIONAL CLASS-C VCO. 96 FIGURE 5.2.2 SCHEMATIC OF DYNAMIC BIASING CLASS-C VCO. 96 FIGURE 5.2.3 SCHEMATIC OF PROPOSED QVCO WITH DYNAMIC BIASING CLASS-C OSCILLATORS. 97 FIGURE 5.3.1 DIE PHOTOGRAPH. 98 FIGURE 5.3.2 MEASURED FREQUENCY TUNING RANGE OF THE PROPOSED VCO CIRCUIT. 98 FIGURE 5.3.3 MEASURED OUTPUT SPECTRUM OF THE PROPOSED QVCO.VDD = 1.1 V ,VTUNE = 0.7 V , VBIAS = 1V. 99 FIGURE 5.3.4 MEASURED OUTPUT PHASE NOISE OF THE PROPOSED QVCO. VDD = 1.1 V ,VTUNE = 0.7 V , VBIAS = 1V AND FOSC = 2.04GHZ. 99 FIGURE 5.3.5 SIMULATION THE VCLASS-C , VG OF THE M8, M9 AND VTH OF THE M8, M9. 100 FIGURE 5.3.6 MEASURE OUTPUT WAVEFORM OF THE I AND Q CHANNELS. VDD = 1.1 V, VTUNE = 0 V AND FOSC = 1.978GHZ. 101 FIGURE 6.2.1 SCHEMATIC OF PROPOSED CLASS-C VCO. 104 FIGURE 6.2.2 (A) SIMULATED DRAIN, GATE, SOURCE VOLTAGES OF M1 AND (B) SIMULATED DRAIN, GATE, SOURCE VOLTAGES OF M3 FOR THE PROPOSED VCO. VDD = 1.2 V, VTUNE = 2.0 V. VBIAS = 0.5 V. 105 FIGURE 6.2.3 SIMULATED IMPEDANCE OF THE TAIL RESONATOR. 106 FIGURE 6.2.4 LAYOUT OF THE DESIGNED THREE-PATH PARALLEL INDUCTOR WITH A REFERENCE INDUCTOR. 107 FIGURE 6.2.5 SIMULATED L AND Q CHARACTERISTICS OF THE DESIGNED MULTIPATH (MP) INDUCTOR AND A CONVENTIONAL INDUCTOR. 107 FIGURE 6.2.6 SIMULATED PHASE NOISE OF THE VCO WITH AND WITHOUT THE TAIL RESONATORS. VDD = 1.2V, VTUNE = 0 V. VBIAS = 0.5 V. 109 FIGURE 6.3.1 DIE PHOTOGRAPH 110 FIGURE 6.3.2 MEASURED OUTPUT SPECTRUM OF THE PROPOSED VCO. VDD = 1.2 V, VTUNE = 0.0 V. VBIAS = 0.33 V. 111 FIGURE 6.3.3 MEASURED OUTPUT PHASE NOISE OF THE PROPOSED VCO. VDD = 1.2 V, VTUNE = 0.0 V AND FOSC = 2.48GHZ. 111 FIGURE 6.3.4 MEASURED PHASE NOISE AND OSCILLATION FREQUENCY OF THE PROPOSED VCO CIRCUIT. 112   List of Tables TABLE I THREE TOPOLOGIES OF LC OSCILLATORS. 28 TABLE II PERFORMANCE COMPARISON OF VCO 94 TABLE III COMPARISON OF QVCO PERFORMANCE 102 TABLE IV PERFORMANCE COMPARISON OF VCO 113

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