在無線通訊系統中，工作於相位頻率鎖相迴路的頻率合成器扮演著重要的角色，其內部包含了環型震盪器(RO)、倍頻器(FD)、頻率相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、電壓控制振盪器(VCO)或電流控制震盪器(CCO)及除頻器(FD)。Phase-Locked Loop (PLL)組成子電路中，又以電壓控制震盪器(VCO)和除頻器(FD)特性最為重要，其中的電路主要追求低的相位雜訊、低的消耗功率及較寬的鎖定頻率範圍於除頻器。所以本篇論文呈現出各種高性能的電壓控震盪器和頻率鎖相迴路(PLL)的設計。

首先，我們設計一個新架構的低相位雜訊的Push-Pull架構的電壓控制振盪器（VCO），命名為使用單片8字型電感為基礎之推挽式低相位雜訊電壓控制震盪器，此電壓控制震盪器使用台積電0.18 μm 1P6M CMOS 製程，並且電壓控制震盪器使用單片8字型互感耦合的電感方式及Push-Pull的VCO架構組成。此電壓控制震盪器可以在低電壓源模式下運行，最佳的偏壓範圍條件產生較優良的相位雜訊、低功耗及消除諧波頻率。在包含了輸出緩衝器的條件下，其消耗功率圍0.432 mW，相位雜訊在1 MHz的量測基準點上，可達到-124.932 dBc/Hz，此中心頻率為2.99 GHz，整體的 Figure Of Merit (FOM)為 198.091 dBc/Hz.。
第二個設計一個整合兩個差分放大器的低相位雜訊新架構雙環形振盪器（Double Ring Oscillator），使用台積電0.18 μm SiGe BiCMOS 製程並命名為低相位雜訊重複使用緩衝器之BiCMOS震盪器，整個設計面積為1.1  1.2 mm^2，第一個放大器使用HBT，並且疊構在nMOSFET之上，第二個放大器包含了輸出緩衝器的nMOSFET，使得輸出的緩衝器可以再次的利用，也可將整體的電源消耗大幅的降低，達到2.65 mW，並且提供了非常低的相位雜訊，在中心頻率為4.19 MHz，其相位雜訊可達到在1 MHz的量測基準點上-128.81 dBc/Hz，整體的FOM可達到 -194.08 dBc/Hz。

第三個設計一個低消耗及低相位雜訊class-D的倍頻器，使用台積電0.18 μm SiGe BiCMOS 製程，整個設計面積為1  1 mm^2。此設計使用0.4 V電源，n-core 震盪器於正常的閾值電壓輸出2.8 GHz 頻率，倍頻器使用兩組電容及電感交叉耦合對來組成負阻抗，電容及電感交叉耦合增強對其中的主動元件閘極端偏壓，短暫切換FET在深截止區啟動class-D模式。

最後設計一個完整的電流控制震盪器(CCO)的鎖相迴路，使用台積電0.18 μm CMOS 製程，整個設計面積為1.173  0.644 mm^2，工作電壓為1.8 V。此PLL包含了七個功能方塊，經由外部的Crystal產生的輸入參考頻率24MHz，再透過電流控制震盪器，使得鎖相迴路鎖定在2.4G的震盪頻率。此PLL內部的功能方塊包含了環形震盪器 (RO)，產生24MHz的參考頻率，透過倍頻器 (FD)將頻率倍頻到48MHz，再透過相位頻率偵測器Phase Frequency Detector (PFD)來判斷頻率與相位是否與CCO相同，經由充電器 Charge Pump (CP)及低通濾波器 (LPF)，提供調整電壓來調整電流控制震盪器所震盪的頻率，再經由除五十的電路 Divider by 50 (D50)，產生48MHz給PFD做頻率相位偵測，電流控制震盪器可調整頻率範圍為1.635 GHz ~ 2.775 GHz，消耗功率於7.335mW，Phase Noise為-81.2537 dBc/Hz，整體鎖相迴路的消耗功率在2.4 GHz為18.775mW。

The frequency synthesizer, working in PLL circuit, is an important role in the wireless communication system, its blocks consist of Ring Oscillator (RO), Frequency Doubler (FD), Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage-Controlled Oscillator (VCO) or Current-Controlled Oscillator (CCO), and Frequency Divider by N (FD). The VCO and Frequency Divider (FD) also are very important designs in PLL circuits to pursue low power consumption, low phase noise, and a wide locking range of divider. Therefore, this dissertation presents the design of high-performance VCO and PLL.

The first design presents a low-phase noise Voltage-Controlled Oscillator (VCO) deploys Push-Pull architecture and is named as Low Phase Noise Push-Pull Architecture Voltage-Controlled Oscillator with 8-shaped Monolithic Transformer Base in the TSMC standard 0.18 μm 1P6M CMOS processes. The die area is 0.798  0.762 mm2. This architecture builds up an 8-shaped negative coupling inductor and Push-Pull VCO architecture to reduce the power dissipation and to eliminate the harmonic frequency. Its power consumption of 0.432 mW with output buffer current, the phase noise is -124.932 dBc/Hz at 1 MHz offset frequency from the center frequency 2.99 GHz. The Figure of Merit (FOM) is -198.091 dBc/Hz.
The second design presents a low-phase noise Voltage-Controlled Oscillator (VCO) integrated with two differential amplifiers in new Double Ring Oscillator architecture and is named a Low Phase Noise Buffer-Reused BiCMOS Oscillator in the TSMC proprietary 0.18 μm SiGe BiCMOS processes. The die area is 1.1  1.2 mm2. The first amplifier uses HBT stacking on nMOSFET, and the second amplifier uses an nMOSFET amplifier which is an output buffer reused and reduces the power dissipation. Its power consumption of 2.65 mW with output buffer current, the phase noise is -128.81 dBc/Hz at 1 MHz offset frequency from the center frequency 4.19 GHz. The FOM is -194.08 dBc/Hz.
The third design presents a class-D oscillator with frequency doubler implemented in the TSMC standard 0.18 μm SiGe BiCMOS processes. The die area is 1  1 mm2. At the supply voltage of 0.4 V below the normal threshold voltage, the n-core oscillator outputs at a 2.80 GHz frequency. This class-D oscillator with frequency doubler is made of a parallel LC resonator with TSMC proprietary inductors, and a capacitive cross-coupled nMOSFET pair with inductive gate voltage booting, which enables the class-D mode operation by switching the FETs to the deep cut-off region in a shorter time.
Finally, this presents a fully integrated Phase-Locked Loop (PLL) with a Current-Controlled Oscillator in TSMC standard 0.18μm CMOS process. The die area is 1.173  0.644 mm2. Its operating voltage is 1.8V. This PLL consists of 7 functional blocks which are deployed 24 MHz Ring oscillator, Frequency Doubler (FD), Phase Frequency Detector, Charge Pump, Low Pass Filter (LPF), Current Controlled Oscillator (CCO), and Divider by 50 (D50). The tuning range of CCO is 1.635 GHz~2.775 GHz; meanwhile, the power consumption of CCO is 7.335 mW, and phase noise is -81.2537 dBc/Hz. The total power consumption of PLL is 18.775 mW. This PLL is successfully locked at a 2.4 GHz output frequency.

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