To increase the write performance on MLC
ash memory, the conventional
method will convert the MLC block to the SLC-mode block. Because the
SLC-mode block only uses two threshold voltage status, it has better write
performance. Then, the SLC-mode block will be used to absorb the por-
tion coming request. By this way, it also increases write amplication. We
proposed a new idea to reduce write amplication in this case. The paper
has two ways to achieve the goal. The rst is the encoding scheme. The
second is the SLC block allocation. The encoding scheme changes the bits
of each voltage status. The SLC block allocation will use a new block mode
(refer as SLC-mode reprogram) to allocate. The two ways can reduce write
amplication and increase performance. We use the average write response
time to evaluate performance. The block erase count and write amplication
are used to evaluate the
ash memory lifetime. Evaluation shows the write
amplication can reduce the most up to 55% in our scheme. For the average
write response time, our proposed scheme can reduce the most up to 51%.
For the block erase count, our proposed scheme can reduce the most up to
46%.

To increase the write performance on MLC
ash memory, the conventional
method will convert the MLC block to the SLC-mode block. Because the
SLC-mode block only uses two threshold voltage status, it has better write
performance. Then, the SLC-mode block will be used to absorb the por-
tion coming request. By this way, it also increases write amplication. We
proposed a new idea to reduce write amplication in this case. The paper
has two ways to achieve the goal. The rst is the encoding scheme. The
second is the SLC block allocation. The encoding scheme changes the bits
of each voltage status. The SLC block allocation will use a new block mode
(refer as SLC-mode reprogram) to allocate. The two ways can reduce write
amplication and increase performance. We use the average write response
time to evaluate performance. The block erase count and write amplication
are used to evaluate the
ash memory lifetime. Evaluation shows the write
amplication can reduce the most up to 55% in our scheme. For the average
write response time, our proposed scheme can reduce the most up to 51%.
For the block erase count, our proposed scheme can reduce the most up to
46%.

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