本論文主要目的是整合跨時域的天線模組與FPGA板，基於802.11 a/g 網路通訊協定的嵌入式無線收發平台。論文內容主要描述在跨時域上天線模組與FPGA版時所解決的問題以及Xilinx開發軟體上的應用，如何透過分析結果去判斷問題進而解決。整塊系統是由AD-FMCOMMS3(ad9361)天線模組配合Virtex6 FPGA 開發板(xc6vlx240t/ff1156/-2)，先藉由FPGA板上震盪器啟用自己設計之初始化硬體，其後由天線模組之震盪器做為系統時脈推動收發系統以達到最佳同步化解決跨時域上的資料同步問題。

This thesis proposes the synchronization of clock domain crossing between RF module and FPGA. SoC become more complex, and different frequency signals merge into one chip. Therefore, the synchronization of clock domain is challenging..
If FPGA and RF module have two different clock sources, data crossing different clock domains may not be latched normally. Using asynchronization FIFO can solve this problem. However, using asynchronous FIFO may lead to another problem: data loss, which increases packet error rate. In this paper, we solve this problem by forcing FPGA and RF module to use the same clock source. To initialize the clock source, we use on-chip microblaze and/or hardware module. FGPA resource utilization for using these two modules are compared.

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