第五代行動通訊系統(5th Generation mobile network, 5G)即將來臨，許多地區已經開始建設5G的行動網路，但5G使用了比4G更高的頻段，頻段的提高便會造成覆蓋率降低，因此必須以增加射頻單元(Radio Unit, RU)的方式進行彌補，以往的電信設備僅由少數公司提供，並且使用了封閉的系統，不同品牌之間的相容性不佳，因此在設備的擴充上容易受到限制。開放式無線接取網路(Open Radio Access Network, O-RAN)聯盟由眾多電信營運商與電信設備商所組成，其目標是開放目前封閉的電信設備環境，O-RAN聯盟針對無線接取網路(Radio Access Network, RAN)制定了標準化的規範，任何廠商都能根據規格設計與製造自己的電信設備，藉由這個標準化的規範，不同廠牌的設備也能互相相容，行動網路也能以更靈活的方式進行建設。本論文將設計一個符合O-RAN規範的射頻單元(O-RU)，此O-RU具有控制平面與資料平面分離的設計，同時還有同步平面用於時間與頻率同步，本論文將會以現場可程式化邏輯閘陣列(Field Programmable Gate Array, FPGA)進行功能驗證，利用FPGA方便調整內部電路的特性，未來若是遇到新規格的發布或是需要進行功能的增減，皆能以較少的時間達成電路的更新。

The 5th Generation mobile network (5G) is around the corner. The construction of the 5G mobile network has been on at many places. However, the frequency band used by 5G is higher than 4G. Increased frequency band will cause a reduction in coverage. In order to keep the same coverage, the addition of Radio Unit (RU) is necessary. In the past, only a few companies provided telecommunication equipment, and most of them were closed system. The products of two different brands are incompatible at most times. Therefore, it is usually restricted when expanding equipment. The Open Radio Access Network (O-RAN) alliance is composed of many telecommunications operators and equipment vendors, and its goal is to open the closed telecommunication equipment environment. The O-RAN alliance has established the standardized specifications of Radio Access Network (RAN). Any manufacturer can design and produce their own telecommunications equipment according to the specifications. Through these standardized specifications, devices of different brands can also be compatible with each other, and mobile networks can also be constructed in a more flexible manner. In this thesis, we will design a O-RAN Radio Unit (O-RU) that conforms to the O-RAN specifications. This O-RU has a design where the control plane and the data plane are separated, and there is also a synchronization plane for time and frequency synchronization. This thesis will use the Field Programmable Gate Array (FPGA) for implementation and functional verification of O-RU. Taking advantage of the characteristic that the internal circuits in FPGA can be adjusted conveniently, if the new specifications are released or function modification is needed in the future, the circuits update can be achieved in less time.

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