研究生: |
陳世崴 Shi-Wei Chen |
---|---|
論文名稱: |
利用脈波縮減/增加機制之工作週期校正電路 Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism |
指導教授: |
陳伯奇
Poki Chen |
口試委員: |
宋國明
none 羅有綱 none 姚嘉瑜 none |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 中文 |
論文頁數: | 110 |
中文關鍵詞: | 工作週期校正 、脈波寬度縮減/增加機制 、低功率 、寬範圍 |
外文關鍵詞: | duty cycle corrector, pulse shrinking/stretching mechanism, low power, wide range |
相關次數: | 點閱:473 下載:2 |
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工作週期校正電路(Duty Cycle Corrector,DCC)的功能為調整50%的工作週期,廣泛地使用在雙倍資料速度同步動態隨機存取記憶體(Double Data Rate SDRAM,DDR SDRAM)、雙取樣類比至數位轉換器(Double-Sampling ADC)、延遲鎖定迴路(Delay Locked Loop,DLL)與鎖相迴路(Phase Locked Loop,PLL)等需要時脈訊號的上升緣與下降緣的運作。工作週期校正電路在架構上可分為數位式與類比式。數位式架構又可分為回授型與非回授型兩種。類比式架構通常為回授型,以較長的鎖定時間來獲得較精準的工作週期校正。
在本篇論文中,提出一簡單類比負回授架構之工作週期校正電路,利用脈波縮減/增加機制(Pulse Shrinking/Stretching Mechanism)達到工作週期的校正。所提及電路不用如數位式架構需要許多複雜的電路架構,以及類比式充電幫浦所產生的問題,就能達成工作週期的校正。
利用脈波縮減/增加機制之工作週期校正電路(Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism)已經實現。所提及的工作週期校正電路經由TSMC 0.35μm 標準CMOS製程(TSMC 0.35μm standard CMOS process)製造完成。具有廣的輸入工作週期範圍30%~70%與寬的輸入頻率範圍3MHz~660MHz,且工作週期校正誤差在-1%與1%之間,因此能使電路更適合於超寬頻(Ultra Wide Band)的應用上。此晶片面積只有0.3 × 0.2 mm2,而功率消耗在550 MHz操作頻率時為1.1 mW。
The duty cycle correctors (DCCs) are widely used to adjust the clock duty cycle to 50% for DDR (double data rate)-SDRAM, double-sampling ADC, DLL (delay locked loop) and PLL (phase locked loop), where both clock rising and falling edges are used for operation. There are two major categories, digital and analog, for DCC realization in literatures. The digital DCCs can be further classified into the feedback type and the non-feedback type. The analog DCCs are usually implemented as feedback type to get better duty cycle accuracy at the expense of long locking time.
In this thesis, a simple analog DCC with negative feedback is proposed. The pulse shrinking/stretching mechanism is utilized to achieve the duty cycle correction. Neither the complicated circuit in digital DCCs nor the charge pump in analog ones is required.
A duty cycle corrector based on pulse shrinking/stretching mechanism is presented. The proposed DCC has been fabricated in a TSMC 0.35μm standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is between -1.0% to +1% for the widest frequency operation range of 3MHz~660MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 × 0.2 mm2 and the power consumption is 1.1mW at 550 MHz.
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