本論文主要研究注入鎖定除頻器，以及壓控振盪器。此兩種電路是無線通訊系統中重要的兩種電路，其操作頻率範圍決定頻率合成器之頻寬。一個好的振盪器必須具有低相位雜訊之特性，以避免相鄰頻帶雜訊的混波轉換。注入鎖定除頻器經常被用作高頻除頻器，必須具有寬鎖定範圍之特性。
第一部分提出了一個有三頻帶的寬頻注入鎖定除頻器,用 TSMC 0.18 μm 1P6M CMOS技術完成. 本除二的注入鎖定除頻器是由NMOS交叉耦合對以及六階層的LC槽實現. 在供應電壓為1V時,本電路消耗功率為11.6 mW .該電路主頻帶分別為8.75 GHz(高頻帶) 5.79GHz(中頻帶)以及3.7GHz(低頻帶);除頻範圍分別為17.1 GHz到18.3GHz(高),10.1 GHz到12.7GHz(中),以及6.0 GHz 到7.7GHz(低).本電路可藉由改變可變電容的大小來切換操作頻段.電路面積為0.898×0.980mm2.
其次, 提出的是一個操作於6 GHz的串聯可調阿姆斯壯全N型壓控振盪器,該電路被TSMC 0.18 μm 1P6M CMOS技術完成.該電路是由兩個單端串連阿姆斯壯壓控振盪器組成.當供應電壓為1.3 V時,該電路的的相位雜訊在離主頻1 MHz處為-125.88 dBc/Hz,主頻為6.06 GHz. 本電路之figure of merit(FOM)為-192.8 dBc/Hz.
最後,呈現一個雙頻帶P型壓控振盪器.該電路由雙共振LC槽以及全P型的交叉偶和對組成.該電路的震盪模態分別為串聯共振(高頻)以及並聯共振(低頻),並可藉由可變電容切換頻帶.該電路的高頻帶操作在7 GHz低頻帶操作2.9GHz.本電路由TSMC 0.18 μm 1P6M CMOS實現, 在供應電壓為0.65 V時消耗功率為3.003 mW. 本電路面積為0.953×1.0 mm2.

This thesis presents the design of Injection - Locked Frequency Dividers (ILFDs) and voltage-controlled oscillator (VCO) which are two kinds of important sub-circuits in wireless telecommunication systems. Bandwidth of a frequency synthesizer is dominated by operating frequency ranges of these two blocks. A good VCO must exhibit low-phase-noise characteristic to prevent noise in adjacent frequencies from being down-converted or up-converted. We generally apply an injection-locked frequency divider (ILFD) to perform frequency division at high frequency. The wider the locking range is, the better ILFD.
Firstly, we present A triple-band wide operation range divide-by-2 injection-locked frequency divider (ILFD) using a standard the TSMC 0.18 μm 1P6M CMOS technology is presented. The ÷2 ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator with a 6th order LC resonator. The core power consumption of the ILFD core is 11.6 mW at the supply voltage of 1V. The divider’s free-running frequency operates at three frequency bands: 8.75 GHz, 5.79GHz and 3.7GHz, and the ILFD operation range covers a high-band from 17.1 to 18.3GHz, a middle-band from 10.1 to 12.7GHz, and a low-band from 6.0 to 7.7GHz. The band section is obtained by tuning the varactor’s control bias. The chip area is 0.898× 0.980 mm2.
Secondly, A 6 GHz series-tuned Armstrong all nMOS LC-tank voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology consists of two single-ended series-tuned Armstrong LC-tank VCOs. At the supply voltage of 1.3 V, the output phase noise of the VCO is -125.88 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 6.06 GHz, and the figure of merit is -192.8 dBc/Hz. Total VCO core power consumption is 7.46 mW. Tuning range is about 370 MHz, from 5.91 GHz to 6.28 GHz, while the control voltage was tuned from 0 V to 2 V. The chip area is 0.977×0.515 mm2.
Finally, we present a dual-band p-core oscillator. The oscillator consists of a dual-resonance LC resonator and a cross-coupled switching transistor pair and it operates at the high-frequency series-resonant mode and at the low-frequency parallel-resonant mode via varactor switching bias. The oscillator can generate differential signals at the high-band 7GHz and at the low-band 2.9GHz. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and the core power consumption is 3.003 mW at the dc drain-source bias of 0.65 V. The die area of the dual-band VCO is 0.953×1.0 mm2.

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