在本篇論文中，我們基於 New-Old Register Encoding 架構，提出一個效能更佳的架構。主要觀察其不利於效能之設計，根據指令編碼的兩種格式 ─ Two Operands 和 Three Operands ，分別提出其改進方案，使得效能獲得改善，並且保有原先加倍暫存器的好處，讓編譯器或程式設計師可以使用更多的暫存器提高程式的效率。
利用這方法我們提升了原先架構 7 % 的效能， Alpha 微處理器中暫存器的數目增為原本的 8 倍，由原本的 32 顆暫存器增加到 256 顆暫存器，讓 32 位元的指令不受位元的限制，使用到更多的暫存器，編譯器或程式設計師可以使用 256 個暫存器來存放變數或計算結果，提高程式的效率。
在我們提出的方法中，我們需要將原先在組譯器中造成效能低落的程序，提前至編譯器階段處理，這樣的好處是我們可以分析整個程式的關係，進而減少這類情況的發生，此外我們也修改了組譯器來產生更有效率的程式碼。

This paper is based on “New-Old Register Field Encoding” and tried to improve its performance. We proposed two method to remove the extra move95 instructions as many as possible. Therefore, we got better performance and kept the advantages from “New Old Register Field Encoding”. This scheme significantly increase the number of register which can encode 4x~8x registers with same encoding space. More register can make compiler perform more aggressive optimization to improve the performance of program.

[1] Alpha. Apha 21264 Processor Technical Reference Manual.

[2] ARM. ARM Reference Manual.

[3] SimpleScalar.Simple_tutorial.

[4] Henning, John L. SPEC CPU2000: Measuring CPU Performance in the New Millennium, 2000

[5] J.H. Lee, J. Park, S.M. Moon. Securing More Registers with Reduced Instruction Encoding Architectures. In Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA’07), page 417-425, 2007

[6] X. Zhuang, S. Pande. Differential register allocation, In Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, pages 57-70, 2005.
[7] C.H. Chou. Code Generation for Register File with New-Old Banks, 2012

[8] G. J. Chaitin, et. al., Register allocation via coloring, In Computer Languages, Vol. 6, pages 47-57, Jan. 1981.

[9] P. Briggs, K. D. Cooper, and L. Torczon, Improvements to graph coloring register allocation, In ACM Transactions on Programming Languages and Systems, Vol. 16, No. 3, pages 428-455, May 1994.

[10] A. B. Kempe. On the geographical problem of the four colors. In American Journal of Mathematics, 2(1): pages 193-200, 1879.

[11] J. Park and S.M. Moon. Optimistic register coalescing. In ACM Transactions on Programming Languages and Systems, Vol. 26, No. 4, pages 736-765, 2004.

[12] L. George and A.W. Appel. Iterated register coalescing. In ACM Transactions on Programming Languages and Systems, Vol. 18, No. 3, pages 300-324, 1996.

[13] T. Austin, E. Larson, and D. Emst. Simplescalar: An infrastruc-ture for computer system modeling. In IEEE Computer, 35(2):59–67, 2002.

[14] J.A. Swensen and Y.N. Patt, Hierarchical Registers for Scientific Computers, In Proceedings of the 2nd international conference on Supercomputing, pages. 346-353, 1988.

[15] B. Scholz, B. Burgstaller, and J. Xue. Minimizing Bank Selection Instructions for Partitioned Memory Architectures. In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pages.201-211 2006.

[16] Bernhard Scholz and Erik Eckstein. Register Allocation for Irregular Architectures. In Proceedings of the Joint Conference on Languages, Compilers and Tools for Embedded Sysems, pages 139-148. 2002.

[17] Andrew W. Appel and Lal George. Optimal spilling for CISC machines with few registers. In Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation, pages 243–253, 2001.

[18] V. Sarkar and R. Barik. Extended Linear Scan: an Alternate Foundation for Global Register Allocation. In Proceedings of the 16th international conference on Compiler construction (CC’07), pages 141-155, 2007.

[19] J. Park , J. H. Lee and S. M. Moon. Register Allocation for Banked Register File, In Proceedings of the ACM SIGPLAN workshop on Languages, compilers and tools for embedded systems, pages 39-47, 2001.
[20] F. M. Q. Pereira and J. Palsberg. Register allocation by puzzle solving, In Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation, June 07-13, 2008.