此論文聚焦應用於生醫感測使用抗雜訊適應性時域比較器之超低功耗時域類比至數位轉換器，其電路包含雙倍式電壓靴帶式開關、適應式時域比較器、電容式數位至類比轉換器、逐漸逼近式邏輯所組成。逐次逼近類比至數位轉換器近年來很熱門，與其快閃式（Flash）、流水線式（Pipeline）、ΔΣ(Delta-Sigma)式架構相比，此架構在相較易實現低功率消耗、高解析度與面積小，可取得完美的平衡點，這歸功於科技與製程上的突破，許多技術上的門檻及限制因此解決。
類比至數位轉換器的功用，是從輸入類比訊號量化出相對應的數位輸出訊號。一般比較常見的設計是將電壓轉換成數位輸出，一旦改成時域設計，相較電壓域更加省電，普遍常見的時域架構則有電壓控制振盪器、時間至數位轉換器、時域式比較器、數位斜率(Digital Slope)。
本論文使用適應性時域比較器相較傳統時域比較器在效能的表現上更加優異。每一位元的運作會根據輸入相關雜訊(Input-Referred-Noise)做調整。適應式時域比較器相較傳統，增加了差動門檻窗口(Differential Threshold Window, DTW)結構，產生門檻時間來調適工藝電壓溫度（Process-Voltage-Temperature, PVT）變化，降低PVT影響，可有效地降低品質因數(Figure-of-Merit , FoM)，增加抗雜訊能力及提升有效位元數。
本論文提出的超低功耗時域類比至數位轉換器操作在0.6V 取樣頻率為20KS/s，在台灣半導體研究所（TSRI）的幫助下使用的製程為TSMC 0.18μm 1P6M CMOS工藝，量測結果在0.8V，可得到有效位元數(ENOB)為9.0(bit)、信號對雜訊失真比（SNDR）為56.0(dB)、無假訊號動態範圍(SFDR)為67.5(dBc)、功耗為1.82(µW)、品質因數(FoM)為173.1(fJ/c-s)、晶片面積為1.184〖mm〗^2

A 12 bit ultra-low-power time-domain analog-to-digital converters with anti-noise adaptive time-domain comparators for biomedical sensing consisting of double bootstrapped switch, adaptive time domain comparator, capacitive digital-to-analog converter (CDAC), and successive-approximation (SAR) logic is proposed in this thesis. successive-approximation analog-to-digital converter has become very popular in recent years since it is easy to achieve a perfect balance of low power consumption, high accuracy, high resolution, and small area compared to flash, pipeline, delta-sigma. According to the technological and process breakthroughs, many technical barriers and limitations have been solved.
The function of an analog-to-digital converter (ADC) is to quantize the corresponding digital output signal from the analog input signal. With time-domain instead of voltage-doman design, SAR ADC becomes even more energy efficient. The commonly used time-domain blocks are voltage control oscillator（VCO）, time-to-digital converter (TDC), time domain comparator, digital slope.
In this thesis, the adaptive time domain comparators are utilized since each bit is adjusted according to input-referred-noise. The adaptive time domain comparator adds a differential threshold window (DTW) structure to generate the threshold time to adapt the process-voltage-temperature (PVT) generation variation and reduce the PVT impact, which can effectively reduce the figure-of-merit (FoM), increase the anti-noise capability and improve the effective number of bits (ENOB) value.
The proposed ultra low power ADC is designed to operate at 0.6V with a sampling frequency of 20KS/s and implemented in a TSMC 0.18μm 1P6M standard CMOS process with the help of Taiwan Semiconductor Research Institute (TSRI). The measurement results are ENOB equals to 9.0(bit), signal to noise and distortion ration (SNDR) equals to 56.0(dB), spurious free dynamic range (SFDR) equals to 67.5(dBc), power consumption equals to 1.82(µW), FoM equals to 173.1(fJ/c-s) and chip area equals to 1.184(〖mm〗^2).

[1]M. Liu, A. van Roermund and P. Harpe, "A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset," ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 2016, pp. 409-412.
[2]陳博瑋 , “The Analysis and Design of Successive Approximation Analog-to-Digital Converter for Biomedical Applications,” 長庚大學電子工程研究所碩士論文, Aug. 2004.
[3]A. Agnes, E. Bonizzoni, P. Malcovati and F. Maloberti, "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 246-610
[4]P. Chen, C. -C. Chen, J. -C. Zheng and Y. -S. Shen, "A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy," in IEEE Transactions on Nuclear Science, vol. 54, no. 2, pp. 294-302, April 2007.
[5]Po-Chang Wu, SC Circuit Design Techniques,
[6]C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010
[7]Y.-J. Chen, K.-H. Chang, and C.-C. Hsieh, “A 2.02–5.16 fJ/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 357–364, Feb. 2016.
[8]P. J. A. Harpe, C. Zhou, K. Philips and H. de Groot, "A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC," in IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2450-2457, Nov. 2011
[9]C. -C. Liu, M. -C. Huang and Y. -H. Tu, "A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2941-2950, Dec. 2016
[10]X. Zhou, X. Gui, M. Gusev, N. Ackovska, Y. Zhang and L. Geng, "A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, pp. 359-363, Feb. 2022
[11]H. Zhao and F. F. Dai, "A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment," 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1-3
[12]S. -E. Hsieh, C. -K. Ho and C. -C. Hsieh, "A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015, pp. 2429-2432
[13]蘇正文,「Design of CMOS Cyclic TDC-based ADC」。碩士論文, 國立暨南國際大學電機工程學系, 2013。
[14]S. -E. Hsieh, C. -C. Kao and C. -C. Hsieh, "A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization," in IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2763-2771, Oct. 2018.
[15]M. Zhang, C. -H. Chan, Y. Zhu and R. P. Martins, "A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques," in IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3396-3409, Dec. 2019.
[16]S. Y. Wu, L. Du, M. Jiang, N. Ning, Q. Yu and Y. Liu, "A 10-bit 100MS/s time domain Flash-SAR ADC," 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, China, 2014, pp. 1-2.
[17]Yan-Jiun Chen and C. -C. Hsieh, "A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 2014, pp. 1-2
[18]J. P. Mathew, L. Kong and B. Razavi, "A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply," 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan, 2015, pp. C66-C67
[19]Y. Zhang and Z. Zhu, "Recent Advances and Trends in Voltage-Time Domain Hybrid ADCs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 6, pp. 2575-2580
[20]P. Chen, Shen-Luan Liu and Jingshown Wu, "A CMOS pulse-shrinking delay element for time interval measurement," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 954-958, Sept. 2000
[21]H. Chan and G. W. Roberts, "A jitter characterization system using a component-invariant Vernier delay line," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 1, pp. 79-95, Jan. 2004
[22]P. Dudek, S. Szczepanski and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," in IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
[23]R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg and P. T. Balsara, "1.3 V 20ps time-to-digital converter for frequency synthesis in 90-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 3, pp. 220-224, March 2006
[24]Al-Sarawi, Said. (2002). Low power Schmitt trigger circuit. Electronics Letters. 38.
[25]A. Agnes, E. Bonizzoni, P. Malcovati and F. Maloberti, "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 246-610
[26]S. -K. Lee, S. -J. Park, H. -J. Park and J. -Y. Sim, "A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface," in IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 651-659, March 2011.
[27]M. Zhang, C. -H. Chan, Y. Zhu and R. P. Martins, "A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques," in IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3396-3409, Dec. 2019.
[28]D.-R. Oh, J.-I. Kim, D.-S. Jo, W.-C. Kim, D.-J. Chang, and S.-T. Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8μ time-domain interpolating flash ADC with sequential slope-matching offset calibration,” IEEE J. Solid-State Circuits, vol. 54, no. 1, pp. 288–297, Jan. 2019.
[29]S. Zhu, B. Wu, Y. Cai, and Y. Chiu, “A 2-GS/s 8-bit non-interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1172–1183, Apr. 2018.
[30]J. Yoo and C. V. Hoof, Bio-Medical CMOS ICs Integrated Circuits and Systems, 2011, Part 1, pp. 125-155.
[31]S. Zhu, B. Wu, Y. Cai, and Y. Chiu, “A 2-GS/s 8-bit non-interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1172–1183,Apr. 2018.
[32]M. Shim et al., "Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC," in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1077-1090, April 2017
[33] M. Yip and A. P. Chandrakasan, "A resolution-reconfigurable 5-to-10b 0.4-to-1v power scalable sar adc", 2011 IEEE International Solid-State Circuits Conference, pp. 190-192, 2011.
[34]X. Zhou, X. Gui, M. Gusev, N. Ackovska, Y. Zhang, and L. Geng, “A 12-bit 20-kS/s 640-nW SAR ADC with a VCDL-based open-loop timedomain comparator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 69, no. 2, pp. 359–363, Feb. 2022.
[35]M. Sadollahi, K. Hamashita, K. Sobue, and G. C. Temes, “An 11-bit 250-nW 10-kS/s SAR ADC with doubled input range for biomedical applications,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 65, no. 1, pp. 61–72, Jan. 2018.
[36]C. -E. Hsieh and S. -I. Liu, "A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS," 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), KaoHsiung, Taiwan, 2014, pp. 325-328, doi: 10.1109/ASSCC.2014.
[37]DrCYChen and Hsin-Shu Chen, Advanced Analog Integrated Circuits, NTU, 2022.
[38]Behzad Razavi, Microelectronics, 2/e, Wiley, 2014.
[39]S. Henzler, Time-to-Digital Converters, Netherlands:Springer, 2010.
[40]Yung-Hui Chung, VLSI Data Conversion ICs, 2021.
[41]Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2/e, McGraw-Hill Education, pp.228-239, 2016.
[42]R. Jacob Baker, Circuit Design, Layout, and Simulation ,4/e (Hardcover), Wiley, 2019.