現今超大型積體電路(VLSI)設計為了滿足電路對於性能、面積和功率消耗嚴格的要求，如何在設計流程早期階段提供準確的功率消耗估算，對於現代超大型積體電路設計中晶片上系統(SoC)的設計探索和驗證至關重要。先前的研究作法利用暫存器的轉態頻率(switching activity)來估計功率消耗，並且利用測得的參數進行曲線擬合技術（例如回歸等方式）或是使用深度學習方式為每個子電路建立功率估計模型，來估計電路的功率消耗，然而先前作法沒有考慮到在訓練階段取得模型訓練標籤是相當費時的，如何有效減少訓練資料的數量，以及提升模型的預測準確率是我們的目標。本篇論文使用基於主動式深度學習方法進行設計流程早期的功率分析，並提出兩大改善方法。第一，使用主動學習方法(Active learning)對所有資料進行分群，並挑選適合的訓練資料，減少取得模型訓練標籤時所需消耗大量時間；第二，本篇論文對於故障功率(Glitch Power)提出新的資料特徵表示方法，以及對於多周期延遲路徑(Multi-cycle delay path)問題提出RNN 自動編碼器(Auto-encoder)解決方法以提升深度學習估計準確率。透過實驗結果顯示使用我們提出的資料特徵以及主動學習的挑選機制，可以使測試資料有效的收斂，並且提升總體的準確率，對於小的電路在挑選10%訓練資料下最多可以提升32%準確率，對於另外兩個較大的電路在挑選40%訓練資料下，準確率分別提升了75.9%以及47.5%。分別評估加入故障功率或是加入RNN自動編碼器對於準確率的影響，故障功率提出的特徵資料表示法，在小電路測試中挑選80%訓練資料下可以再額外提升46.2%準確率；使用RNN自動編碼器則可以在較大電路中挑選20%訓練資料下再額外提升44.9%準確率。

In order to meet the stringent requirements of circuit performance, area and power consumption in current VLSI designs, how to provide accurate power estimation in the early stage of the design flow is very important for the design exploration and verification of the system-on-chip (SoC) in modern ultra-large integrated circuits. Previous research methods used the switching activities of registers to estimate power consumption, and they used the measured parameters to perform curve fitting techniques (such as regression) or use deep learning method to build a power estimation model for each sub-circuit to estimate the circuit power consumption. However, the previous methods did not take into account that it is very time-consuming to obtain model training labels in the training phase. How to effectively reduce the numbers of training data and improve the accuracy motivates this research work. We use active learning-based deep learning method to perform power estimation in the early stage design flow, and propose two enhancement methods. First, we use active learning to cluster all data and select suitable training data to reduce the time required to obtain model training labels; Second, we propose a new feature representation method for Glitch Power, and an RNN Auto-encoder solution for the multi-cycle delay path problem is proposed to improve the accuracy of power estimation. The experimental results show that the use of our proposed features representation and active learning selection mechanism can effectively converge the testing data and improve the overall accuracy. For small circuit, selecting 10% of the training data can increase the accuracy by 32%. For the other two larger circuits, selecting 40% of the training data and the accuracy is increased by 75.9% and 47.5%. Consider the additional effects of using glitch power and RNN auto-encoders respectively. Considering the feature data representation method proposed by the glitch power, selecting 80% of the training data in the small circuit can further increase the accuracy by 46.2%. Considering the use of RNN auto-encoder can further improve the accuracy of 44.9% in larger circuits, when selecting 20% of the training data.

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