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研究生： 王威竣
Wei-chun Wang
論文名稱： 利用標準CMOS製程實現光積體電路的可行性評估
Evaluation for Designing Optoelectronic Integrated Circuits with standard CMOS process
指導教授： 李三良
San-Liang Lee
口試委員: 吳靜雄
Jingshown Wu
林清富
Ching-Fuh Lin
陳伯奇
Poki Chen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 中文
論文頁數： 66
中文關鍵詞： 光電積體電路 、矽光子
外文關鍵詞： CMOS photonics, opto-electronic integrated circuits
相關次數： 點閱：350  下載：13 
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  •  上一筆

    • 本論文探討利用國內晶圓廠的標準Bulk CMOS 製程實現光電積體電路的可能性，我們選擇標準0.18 μm CMOS製程中的多晶矽層作為光學波導，並且以微機電(MEMS)後製程將光學波導下方的矽基板挖空，以達到良好的光侷限效果。在我們設計光學元件的過程中，皆考量到標準0.18 μm CMOS製程的限制，並且能夠通過物理驗證(DRC)，由於我們佈局光學元件是使用標準電路佈局軟體Cadence-Virtuoso，因此我們所設計的光學元件能夠輕易的與電路作整合。
    本實驗室已取得二批在標準0.18 μm CMOS製程下線的成果晶片，論文中除了討論佈局和實體晶片的誤差外，亦會討論兩家晶圓廠製程結果的不同。由成果晶片所得到的製程資訊，將能夠作為往後設計及改良光學元件的參考。

    We utilize the polysilicon, which is typically used as the gate material for MOS devices in standard bulk CMOS process, as the optical waveguide in our proposed OEIC configuration. To ensure good optical confinement, a post MEMS process is conducted to create air cavity underneath the waveguide. We then build-up the basic and functional photonic device library using various numerical tools while still meet the design rules defined by the standard CMOS process. For easy integration with electronic circuits, photonic device layout is carried out using computer-aid design software Cadence-Virtuoso, and various layout tricks are explored. We have received two photonic CMOS chips made by standard foundry process. The preliminary results show the feasibility of this approach. Although device characterization is still proceeding, the fabricated chip morphology can be treated as important experiences for the following investigation.

    目錄 摘要......................................................I Abstract...................................................II 致謝.....................................................III 目錄.....................................................IV 圖表索引.................................................VI 第一章 導論...............................................1 1-1前言............................................1 1-2研究動機........................................1 1-3光電積體電路研發平台比較........................2 1-4 論文架構.......................................5 第二章 光學元件設計及模擬.................................6 2-1標準0.18 μm CMOS製程架構.......................6 2-2光學波導模擬與分析..............................8 2-2.1光學波導設計...............................8 2-2.2彎曲波導的光侷限效果......................12 2-2.3錐形波導設計..............................14 2-2.4光柵耦合器設計............................17 2-2.5多模干涉光耦合器..........................21 2-2.6 方向耦合器...............................25 2-2.7 運用環形共振器設計八通道分波多工濾波器...27 第三章 光學元件佈局設計..................................33 3-1 設計流程......................................33 3-2 基本光學波導佈局..............................35 3-3 彎曲波導、多模干涉光耦合器、方向耦合器佈局....39 3-4分波多工環形濾波器佈局.........................44 第四章 標準CMOS製程結果................................48 4-1下線成果.......................................48 4-2 A晶圓廠晶片...................................48 4-2 A晶圓廠 MEMS後製程晶片......................51 4-3 B晶圓廠MEMS後製程晶片.......................54 4-4後製程去除矽基板...............................59 4-5量測規劃.......................................63 第五章 結果與討論........................................65 5-1 成果與討論....................................65 5-2 未來研究方向..................................66 參考文獻.................................................67

    參考文獻
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