近年來，由於無線通訊的快速發展，加上半導體的日益成熟，促使現代化的無線產品需求，以及在消費市場主導下講究輕、薄、短、小以及低價位下，加速射頻積體電路(RFIC)的發展熱潮，如何利用CMOS製程提供更高度的整合便是現在的主要課題，藉由砷化鎵(GaAs)與CMOS的比較，進而了解製程的差異，以便進行改善。
本論文分為兩個部份，第一部分是以TSMC 0.18μm 1P6M CMOS 製程設計應用於802.11a之5.2GHz CMOS 接收機前端電路，在接收機的規劃上採取直接降頻式的接收機架構設計方式，設計出5.2GHz低雜訊放大器以及兩組降頻混波器，模擬結果低雜訊放大器增益為12.8dB、S11為-28.23dB、輸入P1dB為9.3dBm、IIP3為10.5dBm、雜訊指數為2.71dB，混波器方面轉換增益13.9dBm、SSB雜訊指數13.2dB、IIP3為5.2dBm。而第二部份則為製作一3-10GHz 超寬頻低雜訊放大器，低雜訊放大器的模擬增益在3-10GGHz頻段內約8-13dB，S11方面則皆小於-10dB，雜訊指數方面皆小於5dB，IIP3在6GHz的頻段為-7.5dBm，P1dB在6GHz的頻段則為-18.4dBm。

In recent years, with the rapid development of wireless communication as well as the maturation of semi-conductor technologies and industries, there is a substantial increase in customer demand for modern wireless products that are light, thin, short, small and low cost. The development of radio frequency integrated circuits is accelerated correspondingly. As the result, higher integration of CMOS process is now becoming a major issue. Through the comparison between GaAs and CMOS processes, we are able to understand their differences in nature and develop methodologies to deal with corresponding design problems.

The thesis is divided into two major parts. One is the design of an IEEE 802.11a CMOS 5.2GHz receiver front-end circuit in TSMC 0.18μm 1P6M CMOS process. The receiver is designed with direct conversion architecture which consists of a 5.2GHz LNA and two down conversion mixers. The simulation result of the LNA exhibits a gain of 12.8dB, a S11 of -28.23dB, an input P1dB of 9.3dBm, an IIP3 of 10.5dBm, and a NF of 2.71dB. The down conversion mixer exhibits a conversion gain of 13.9dBm, a SSB NF of 13.2dB and an IIP3 of 5.2dBm. The other is the development of a 3-10GHz UWB LNA. The simulation result of the UWB LNA shows a gain of 8-13dB, a S11 less than -10dB, a NF less than 5dB, an IIP3 -7.5dBm at 6GHz and a P1dB of -18.4dBm at 6GHz.

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