時下電子系統之參考時脈通常是由鎖相迴路或延遲鎖定迴路倍頻產生，由於鎖相迴路或延遲鎖定迴路的輸出訊號的工作週期限於製程變異種種因素很難做到50%，對雙倍資料速度同步動態隨機存取記憶體(Double Data Rate SDRAM、簡稱DDR SDRAM)，雙取樣類比至數位轉換器(Double-Sampling ADC)，動態邏輯電路(Dynamic Logic)，半速率時脈資料回復電路(Clock Data Recovery、簡稱CDR)等需要時脈訊號的上升邊緣或下降邊緣皆能運作的電路而言，會相當嚴重地影響其工作效能。此時，便需利用工作週期校正電路將參考時脈之工作週期校正回50%，其重要性可見一般。
工作週期校正電路在架構上可分為數位式與類比式兩種，其中數位式架構又可分為回授式與非回授式，鎖定速度快但準確性較差，類比式架構通常以回授式為主，鎖定速度較慢但卻可達到較高的準確性。
本論文實現一個以循序逼近負載電容調整延遲線之高精度工作週期校正電路，電路架構屬於數位回授式，不但可以快速鎖定，而且準確性也可和類比式架構相互媲美。本晶片採用TSMC 0.18μm 標準金氧半製程來實現，可校正頻率範圍為1GHz~1.6GHz，可校正工作週期範圍為30%~70%，校正後的誤差只有-0.44%~+0.54%。另外，本電路理論上僅需8個時脈週期即可校正完成，晶片面積也僅有0.215 × 0.2 mm2，在1GHz情況下，功率消耗為22.5mW，成效卓著。

Nowadys the reference clock of electronic systems or chips is usually generated by phase-locked loop (PLL) or delay-locked loop (DLL). Due to the process, voltage and temperature (PVT) variations, the duty cycle of PLL or DLL output can be hardly achieved as 50%. It will seriously deteriorate the performance of the systems whose both rising and falling edges are used for triggering or strobing, such as Double data rate SDRAM, DDR SRAM, Double-Sampling ADC, Dynamic logic, Clock Data Recovery. The performance of the above systems can be substantially improved by adopting duty cycle correctors to calibrate the duty cycle of the reference clock back to 50%.
Conventionally, the duty cycle correctors can be further divided into analog type and digital type. The digital DCC can also be sub-divided into non-feedback type and feedback type. Digital DCCs of both types own fast locking capability at the expense of relatively poor accuracy. The analog DCC is usually implemented as feedback type whose locking speed is slow owns comparatively high accuracy.
In this thesis, a digital duty cycle corrector based on SAR loading capacitor adjustment will be proposed to achieve both fast locking and high accuracy. The test chips have been fabricated in TSMC 0.18μm standard CMOS process. The operation frequency range is within 1GHz~1.6GHz and the correctable duty cycle range is between 30%~70% respectively. The error measurement is -0.44%~+0.54% which is the best among current DCCs. Theoretically, the duty cycle correction can be completed within 8 reference clocks. The chip area is merely 0.215 x 0.2 mm2 and the power consumption is 22.5mW at 1GHz.

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