隨著科技的進步，3C產品的開發及推廣，已經成為生活必需品了。而射頻積體電路(RFIC)就是這些產品必須用到的技術，例如家電的各式遙控器、電腦手機平板等電子產品，都會使用到。射頻積體電路(RFIC)由功率放大器(Power amplifier)、收發器(Transceiver)以及鎖相迴路(Phase lock loop)所組成。而本篇論文所探討的重點為鎖相迴路(Phase lock loop)中會使用到的壓控震盪器(VCO)、除頻器(FD)以及倍頻器(FM)的部分。
第一部分介紹了採用 tsmc 0.18 μm CMOS 技術的 3.4 GHz 振盪器的設計和測量。 全集成芯片採用閉環雙絞變壓器耦合傳輸線，佔地面積小，僅為1.2×1.2 mm2。 正交特性是通過傳輸線上的行波形成駐波來確保的。 由於使用了雙絞電感無源器件，QVCO 對附近電路產生的遠場干擾更少，耦合效應也更小。 電源電壓為 1.7 V 時，電流消耗為 11.32 mA。 QVCO 的自由運行頻率是可調的。 在 1MHz 頻率偏移處測得的相位噪聲在 3.4 GHz 振盪頻率下為 -125.73 dBc/Hz，所提議 QVCO 的品質因數 (FOM) 為 -185.38 dBc/Hz。
第二部分介紹了一個電流復用倍頻器 (×2 FD)，它形成了一個帶有壓控 VCO 的發送器。 可調諧 21GHz 發射器採用 180 nm BiCMOS 工藝，全晶片佔用面積 0.84×1.163 mm2。 (×2 FD) 使用堆疊在緩衝器上的倍頻器，SiGe HBT 緩衝器提取倍頻器輸出信號。延伸倍頻器的應用設計出使用 0.18 μm CMOS 工藝的 3.7 GHz 有源倍頻器的設計和測量。全集成倍頻芯片佔地1.129×1.1 mm2，包含兩路電路，一路採用雙絞變壓器，節省芯片面積，另一路採用兩個電感。倍頻器使用兩個電流復用倍頻器來增加轉換增益。
最後一部分通過模擬電流重用 CMOS 24 分頻注入鎖定分頻器 (ILFD) 和基於 4 分頻環形振盪器的 ILFD 在電容交叉耦合 LC 6 分頻 ILFD 上進行研究。 台積電 0.18 μm 1P6M CMOS 工藝中的第一個 24 分頻 ILFD 佔據了 1.2×1.198 mm2 的小面積。 仿真顯示環形振盪器 ILFD 具有寬鎖定以跟踪 LC-sub ILFD 的輸出頻率信號。

With the advancement of technology, the development and promotion of 3C products have become necessities of life. The radio frequency integrated circuit (RFIC) is the technology that these products must use. For example, all kinds of remote controllers for home appliances, computers, mobile phones, tablets and other electronic products are used. The radio frequency integrated circuit (RFIC) is composed of a power amplifier, a transceiver and a phase lock loop. The focus of this paper is the voltage-controlled oscillator (VCO), frequency divider (FD) and frequency multiplier (FM) that will be used in the phase lock loop.
The first part presents the design and measurements of a 3.4 GHz oscillator using in the tsmc 0.18 μm CMOS technology. The fully-integrated chip uses a closed-loop twisted transformer-coupled transmission line and occupies a small area of 1.2×1.2 mm2. The quadrature property is ensured by the traveling wave on the transmission line forming a standing wave. As twisted inductive passives are used, the QVCO generates less far-field interference on the near-by circuits and suffers less coupling effect too. At the supply voltage of 1.7 V, the current consumption is 11.32 mA. The free-running frequency of the QVCO is tuneable. The measured phase noise at 1MHz frequency offset is -125.73 dBc/Hz at the oscillation frequency of 3.4 GHz and the figure of merit (FOM) of the proposed QVCO is -185.38 dBc/Hz.
The second part presents a current-reused frequency doubler (×2 FD), which forms a transmitter with a voltage-controlled VCO. The tunable 21GHz transmitter uses the 180 nm BiCMOS process and the fully-integrated chip occupies a die area of 0.84×1.163 mm2. The ×2 FD uses a frequency doubler stacked on a buffer and SiGe HBT buffer extracts the doubler output signal. The application of the doubler is designed and measurements of a 3.7 GHz active frequency doubler using 0.18 μm CMOS process is present. The fully-integrated frequency doubler chip occupies an area of 1.129×1.1 mm2, and it includes two circuits, one circuit uses a twisted transformer to save die area and the other uses two inductors. The frequency doublers uses two current-reused frequency doublers to increase the conversion gain.
The final part studies by simulation the current-reused CMOS divide-by-24 injection-locked frequency dividers (ILFDs) with a divide-by-4 ring-oscillator-based ILFD on a capacitive cross-coupled LC divide-by-6 ILFD. The divide-by-24 ILFD in the tsmc 0.18 μm 1P6M CMOS process occupies a small area of 1.2×1.198 mm2. Simulation shows the ring-oscillator ILFD has wide locking to track the output frequency signal of the LC-sub ILFD.

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