本論文實現一高速中解析度類比數位轉換器，其主要目的是為了了解在高速時會遇到那一些設計上的問題及考量，使用0.18 微米的互補式金氧半製程來實現，其取樣率可高達36MHz，並且採用一冗位元來使轉換器可以容忍一些安定錯
誤，而參考電壓緩衝電路也包含在晶片內部，來降低因晶片封裝打線寄生電感導致參考電壓震盪問題，其面積大小為137.8 X 302.625μm2。當數位跟類比電壓源為1.8V 時，其量測結果的信號雜訊失真比率與無雜散動態範圍最高分別為51.6922 dB 和51.1916 dB，並實現了8.2112 的有效位元數，消耗功率為1.7366mW。另外為了降低功耗，將數位跟類比電壓源降為1.65V 時，其量測結果的信號雜訊失真比率與無雜散動態範圍最高分別為47.6795 dB 和47.3872 dB，並實現了7.5793 的有效位元數，消耗功率為1.3138mW, FoM 為191.35 fJ/conv.-step。
另外本論文提出一適用於生理訊號感測應用之雙旁通切換循序漸進式類比數位轉換器電路設計，其旁通窗實現方式分別由動態鄰近比較器及次類比數位轉換器來實現，增加可以感測的訊號，並維持低功耗，其電路實現於0.18 微米的互補式金氧半製程，面積大小為282.46 X 412μm2。當供應電壓源為0.6V 時，取樣率為100 kS/s，輸入頻率為49.98 kHz 時，其量測結果的信號雜訊失真比率與無雜散動態範圍分別為55.9341 dB 和60.3672 dB，並實現了8.7461 的有效位元數，消耗功率為368.0675 nW，FoM 為8.23 fJ/conv.-step。除此之外，一校正狀態機使用數位合成做在晶片中，使晶片可以在使用前自動校正雙旁通，以避免因旁通過大導致線性度下降，並且一W-2W 數位類比轉換器做在晶片中以提供旁通窗調整電壓，進而不需要外部校正電路及外部旁通窗調整電壓電路。

This thesis implements a high speed, medium resolution ADC, the design proposal is to realize the high-speed ADC design issues and considerations, the ADC is designed in 180 nm CMOS process, which sampling rate is up to 36MHz, one redundancy is adopted to recovering the settling error, and the reference buffer is on-chip to suppressing the reference voltage ringing, which induced from the bounding wire parasitic inductance, the core area is 137.8 X 302.625μm2. When the ADC supply voltages are 1.8V, the measured SNR and SFDR are up to 51.6922 dB and 51.1916 dB, the ENOB is 8.2112 bits, the power consumption is 1.7366 mW. To reducing power consumption, the ADC supply voltages down to 1.65V, the measured SNR and SFDR are up to 47.6795 dB, and 47.3872 dB, the ENOB is 7.5793 bits, the power consumption is 1.3138mW, the FoM is 191.35 fJ/
conv.-step.

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