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研究生： 石博名
Po-Ming Shih
論文名稱： 注入鎖定除四、除七及除十除頻器之研究
Divide-by-4 , Divide-by 7 and Divide-by 10 Injectio-Locked Frequency Dividers
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 張勝良
Sheng-Lyang Jang
黃進芳
Jhin-Fang Huang
莊敏宏
Miin-Horng Juang
溫俊瑜
Jiun-Yu Wen
學位類別： 碩士
Master
系所名稱： 電資學院 - 光電工程研究所
Graduate Institute of Electro-Optical Engineering
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 154
中文關鍵詞： 壓控振盪器 、注入鎖定除頻器 、環型振盪器
外文關鍵詞： CML
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    • 　　隨著無線通訊系統迅速的發展，各式頻率合成器被研發出來，又以系統單晶片(System-On-Chip)為主要趨勢。其中鎖相迴路(Phase-Locked-Loop,PLL)在眾多領域有廣大的應用，如無線通信、數位電視、廣播等。在無線通信系統中，PLL的特性非常重要，其內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，上述之中以壓控振盪器與除頻器為核心電路，而本論文主要研究三種不同的注入鎖定除頻器設計。
    　　首先，第一部分我們研究一個使用電容交叉耦合式之除四注入鎖定除頻器是由環性震盪除二除頻器疊接於LC除二注入鎖定除頻器之上的架構，除四注入鎖定除頻器是使用台積電BICMOS 0.18微米製程。在0dBm的注入功率下有6.1GHz到10.9GHz的鎖頻範圍，功率消耗為8.24mW，無變容器的注入鎖定除四除頻器有較小的晶片面積0.939×0.728 mm2。
    　　接著，第二部份我們研究一個台積電CMOS 0.18微米製程的寬頻帶除七LC注入鎖定除頻器。此除頻器主要使用三個螺旋電感和寄生的電容作為諧振器，其中包含一組電容交叉耦合MOSFET開關與兩個電感串連的兩個注入MOSFET。晶片面積為1.084 ×1.042 mm2，鎖頻範圍從15.7GHz到17.9GHz共有2.2GHz，功率消耗為9mW。
    　　最後，這篇論文提出一個台積電CMOS 0.18微米製程的注入鎖定除十除頻器，此除頻器使用CML (current-mode logic) 除二除頻器疊接使用電容交叉耦合式之除五注入鎖定除頻器所構成；CML則為在flip-flop啟用上緣clock輸出切換到輸入，以致於輸出頻率為輸入的一半；且負載較為小，則有較小的RC延遲，但需要提高電壓來補償下降的迴路增益，做為功耗與延遲之tradeoff。因此使用CML疊接ILFD，讓直流和交流電流可以更有效使用。疊接的除頻器在不同的操作中選擇適當的頻率並以適度的直流消耗實現適度的頻帶寬。在注入強度為0dBm的情況下有1.25GHz的鎖頻範圍從15GHz到16.25GHz，功率消耗為12.5mW，並且具有除六的功能，晶片面積為1.2x1.2 mm2。

    　　With the rapid development of wireless communication systems, various frequency synthesizers have been developed, with system-on-chip as the main trend. Among them, Phase-Locked-Loop (PLL) has a wide range of applications in many fields, such as wireless communication, digital TV, and broadcasting. In wireless communication systems, the characteristics of the PLL are very important, including the phase detector (PFD), charging pump (CP), loop filter (LF), voltage controlled oscillator (VCO), and frequency divider ( FD), the above-mentioned voltage-controlled oscillator and frequency divider are the core circuits, and this paper mainly studies three different injection-locked frequency divider designs.
    　　First, we study a CMOS divide-by-4 injection-locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-2 ILFD. The divide-by-4 ILFD in the TSMC 0.18 μm 3P6M BiCMOS process has a locking range from 6.1 GHz to 10.9 GHz at the power consumption of 8.24 mW. The varactor-less divide-by-4 ILFD and occupies a small area of 0.939×0.7284 mm2.
    　　Secondly, a wide locking range divide-by-7 LC ILFD manufactured in the TSMC 0.18 μm processes. The 7:1 LC ILFD uses three spiral inductors and parasitic capacitors as the resonator, a capacitive cross-coupled switching FETs and two injection FETs in series with two inductors. The die area is 1.084 ×1.042 mm2. The proto-type 0.18 μm CMOS ILFD has the locking range 2.2 GHz from 15.7 GHz to 17.9 GHz at the power consumption of 9 mW.
    　　Finally, a CMOS divide-by-10 injection-locked frequency divider (ILFD) with a divide-by-2 current-mode logic (CML) stacked on a capacitive cross-coupled oscillator used as an LC divide-by-5 ILFD. the divide-by-10 ILFD in the TSMC 0.18 μm 1P6M CMOS process has a locking range 1.25 GHz from 15.0 GHz to 16.25 GHz at the power consumption of 12.5 mW. The divide-by-10 ILFD uses the CML FD with wide locking range to track the input frequency from the LC ILFD output, and occupies a small area of 1.2×1.2 mm2. The ILFD can be used in divide-by-6 mode.

    摘要 Abstract II 致謝 IV Table of Contents V List of Figures IX List of Tables XVII Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Organization 5 Chapter 2 Overview of the Voltage-Controlled Oscillators 7 2.1 Introduction 7 2.2 Theory of Oscillators 9 2.2.1 Positive Feedback (Two-Port) Oscillators 10 2.2.2 Negative Resistance (One-Port) Oscillators 13 2.3 The Classification of Oscillators 16 2.3.1 Ring Oscillator 16 2.3.2 LC-Tank Oscillator 20 2.3.3 Research of RLC Tank 25 2.3.4 Type of LC Oscillator 29 2.4 Design Parameter of Voltage-Controlled Oscillator 37 2.5 Significant Issue of Voltage-Controlled Oscillator 41 2.5.1 Phase Noise 41 2.5.2 The LTI (Linear Time-Invariant) Phase Noise Model 43 2.5.3 The LTV (Linear Time-Variant) Phase Noise Model 44 2.5.4 Quality Factor 48 2.5.5 Figure of Merit [dBc/Hz] 49 2.6 Elements of Semiconductor Process 50 2.6.1 Resistor 50 2.6.2 Inductor 52 2.6.3 Capacitor 62 2.6.4 Varactor 65 Chapter 3 Design of Injection Locked Frequency Divider 73 3.1 Principle of Injection Locked Frequency Divider 75 3.2 Locking Range 77 3.3 A single injection of ILFD 80 Chapter 4 Current-Reused Divide-by-4 Injection-Locked Frequency Divider Using Ring-Oscillator Frequency Divider 82 4.1 Introduction 82 4.2 Circuit Design 87 4.3 Measurement Results and Discussion 90 Chapter 5 Wide Locking Range LC-Tank Divide-by-7 Injection-Locked Frequency Dividers 96 5.1 Introduction 96 5.2 Circuit Design 98 5.3 Measurement Results and Discussion 101 Chapter 6 Divide-by-10 Capacitive Cross-Coupled Injection-Locked Frequency Divider 108 6.1 Introduction 108 6.2 Circuit Design 111 6.3 Measurement Results and Discussion 113 Chapter 7 Conclusions 125 References 127

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