本論文的主題在於探討容誤技術 (Error-Tolerance, ET)，由於現在VLSI 製程的演進使得元件尺寸大幅下降，但也因此在製造過程中發生瑕疵的機率也隨之提昇而使得良率變低。而容誤是一種應用導向 (Application-oriented) 的概念，藉此提昇有效良率。本篇論文針對動量估測 (Motion Estimation, ME) 的硬體架構去做分析，並以inter-level和intra-level兩種架構為例，比較這兩種架構本身對於錯誤的容忍能力。這樣一來對於設計者而言，在設計動量估測的硬體架構時可以選擇對於錯誤容忍度較高的架構去做設計。另外我們提出一個方法，評估在電路中有錯誤發生時對於整體畫面PSNR的衰減程度，藉由這個評估方法，我們只要能夠得到錯誤對運動向量 (Motion Vector, MV) 的影響，就能計算出錯誤對動量估測整體效能的影響程度。此外，我們還提出了一個電路的容誤設計方法，這個方法可以使得電路元件互換角色。像是錯誤發生在PSNR衰減程度較大的部份的時候，我們可以用衰減程度較小的部份去做置換，如此一來可以全面降低錯誤的影響力。把原本所不能接受的錯誤，轉換成可以接受的錯誤。在實驗結果中我們可以看到，在臨限值 (threshold) 等於0.1dB時我們明顯的將不能接受的錯誤下降了40% 以上，並且隨著臨限值的放鬆可以得到更好的效果。除此之外，可接受的錯誤也增加了近 70%，並且只需要額外 1.5% 的硬體成本。

Error-tolerance is an application-oriented paradigm which can be used to improve effective yield for today’s nano-scale fabrication processes. Therefore, in this thesis, we exploit the inherent error tolerance properties for motion estimation (ME) architectures, including the intra-level and the inter-level parallelism architectures. This is helpful for designers to choice a ME architecture which achieves better error resilience when developing video coding architectures. To achieve this goal, a criterion is first proposed to estimate the performance degradation when a fault occurs and evaluate its acceptability. When a fault is evaluated as unacceptable, a reconfiguration mechanism is activated to increase the acceptability of this fault (i.e., change the role of the cell containing the fault for computing less significant data bits). Many unacceptable faults occurred in the original architecture would be regarded as acceptable faults by using the reconfiguration mechanism. Experimental result shows that we reduce 40.6%, 58.1%, and 63.5% unacceptable faults when the threshold values are set to 0.1dB, 0.3dB, and 0.5dB, respectively. Besides, we increase the proportion acceptable faults from 32.8% to 62.5% when the threshold is 0.1dB. Therefore, we enhance about 70% of acceptability. Furthermore, the hardware overhead of the reconfiguration mechanism is about 1.5%.

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