多電子束微影 (Multiple E-beam Lithography) 作為最有希望的次世代微影技術(Next Generation Lithography)，可用來解決傳統電子束的低產量問題。在多電子束微影系統中，一個電路會被分割成許多長條區，且區域之間會有些許的重疊。在智慧邊界(Smart Boundary)的直寫策略中，縫補區(Stitching Region)的電路圖案可以被簡單分配給不同電子束進行直寫。若有無法分配的電路圖案也可以用軟邊界直寫法 (Soft Edge) 交由兩側電子束共同直寫，但有可能產生對準誤差(Position Error)。為了降低產生對準誤差，本篇論文提出一個考慮縫補區的繞線演算法，在規劃走線時就考慮縫補區電路圖案的可製造性，讓使用多電子束微影製程的電路降低對準誤差。本論文首先介紹了多電子束的直寫策略，並說明考慮智慧邊界的繞線演算法架構，包含全域繞線(Global Routing)、階層與軌道指定(Layer/Track Assignment)、細部繞線(Detail Routing)，實驗結果顯示此演算法能減少軟邊界直寫法的使用量，而大量使用智慧邊界直寫法能增加使用多電子束微影製程電路的可製造性。

As one of competitive next generation lithography (NGL), multiple electron beam lithography (MEBL) has been proposed to improve the low throughput issue. For this maskless lithography, each field is split into stripes that are slightly overlapped with each other, and each stripe of layout patterns is written by a single electron beam (e-beam). If a pattern lies on an overlapped region (stitching region) of two neighboring stripes, it can be written by either of the two e-beams, which is known as smart boundary. To avoid layout features written by more than one e-beam and thus suffering from the overlay error between different beams, we propose a full-chip router utilizing smart boundary to minimize stitch-sensitive patterns. Experimental results show that the proposed algorithm can produce stitch-friendly routing solutions and thus greatly improve MEBL manufacturability and yield.

[1] P. Brandt, C. Tranquillin, T. Figueiro, S. Meunier, S. Bayle, A. Fay, M. Milléquant, B. Icard, M. Wieland, “Demonstration of EDA flow for massively parallel e-beam lithography,” in Proceedings of SPIE, vol. 9049, pp. 904915, 2014.
[2] G. de Boer, M. P. Dansberg, R. Jager, J. J. M. Peijster, E. Slot, S. W. H. K. Steenbrink, M. J. Wieland, “MAPPER: progress towards a high volume manufacturing system,” in Proceedings of SPIE, vol. 8680, pp. 86800O, 2013.
[3] I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, “Stitch-aware routing for multiple e-beam lithography,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 3, pp. 471–482, 2015.
[4] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, and David Z. Pan, “Stitch aware detailed placement for multiple E-beam lithography,” in Integration, the VLSI Journal, vol. 58, Pages 47–54, Jun. 2017.
[5] C. Klein et al., “PML2: The maskless multibeam solution for the 22nm node and beyond,” in Proceedings of SPIE, vol. 7271, pp. 72710N, Mar. 2009.
[6] B. J. Lin, “Future of multiple-e-beam direct-write systems,” in Proceedings of SPIE, vol. 8323, pp. 832302, Mar. 2012.
[7] M. A. McChord et al., “REBL: Design progress toward 16 nm half-pitch maskless projection electron beam lithography,” in Proceedings of SPIE, vol. 8323, pp. 832311, Mar. 2012.
[8] M. J. Wieland et al., “MAPPER: High throughput maskless lithography,” in Proceedings of SPIE, vol. 7637, pp. 76370F, Apr. 2010.
[9] H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, “Full-chip routing considering double-via insertion,” in IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 5, pp. 844–857, May 2008.
[10] H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, “A novel wiredensitydriven full-chip routing system for CMP variation control,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 2, pp. 193–206, Feb. 2009.
[11] T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D.-T. Lee, “Crosstalk- and performance-driven multilevel full-chip routing,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 6, pp. 869–878, Jun. 2005.
[12] R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern routing: Use and theory for increasing predictability and avoiding coupling,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 21, no. 7, pp. 777–790, Jul. 2002.
[13] S. Batterywala, N. Shenoy, W. Nicholls, and H. Zhou, “Track assignment: A desirable intermediate step between global routing and detailed routing,” in IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, USA, 2002, pp. 59–66.
[14] D. Wu, J. Hu, and R. N. Mahapatra, “Antenna avoidance in layer assignment,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 4, pp. 734–738, Apr. 2006.
[15] A. Hashimoto, and J. Stevens, “Wire routing by optimizing channel assignment within large apertures,” in Proceedings 8th Design Automation Workshop, pp. 155-169, Jun. 1971.
[16] P. E. Hart, N. J. Nilsson, and B. Raphael, “A formal basis for the heuristic determination of minimum cost paths,” in IEEE transactions on Systems Science and Cybernetics, vol. 4, no. 2, pp. 100–107, Jul. 1968.
[17] (Sep. 1, 2012). The LEDA Package. [Online]. Available: http://www.algorithmic-solutions.com/leda