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研究生: 簡嘉男
Chia-nan Chien
論文名稱: 具同步整流功能之數位控制全橋相移轉換器設計與研製
Research and Implementation of a Digitally Controlled Phase Shift Full Bridge Converter with Synchronous Rectified
指導教授: 劉益華
Yi-Hua Liu
口試委員: 王順忠
none
華志強
none
謝耀慶
Yao-Ching Hsieh
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 中文
論文頁數: 111
中文關鍵詞: 同步整流相移控制全橋轉換器零電壓切換數位控制
外文關鍵詞: synchronous rectification, phase-shift control, full-bridge converter, ZVS, digital signal controller
相關次數: 點閱:389下載:14
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  • 本文提出具同步整流功能之全數位控制全橋相移轉換器(Phase-Shift Full-Bridge Converter, PSFBC),全橋相移轉換器廣泛應用於中、大功率的電源轉換器,本文採用相移控制初級側功率開關,可達零電壓切換,因此實現高效率和高功率密度的要求。次級側整流架構使用同步整流電流倍增整流架構,電流倍增整流器由兩個濾波電感平均分配輸出電流,因此減少了傳導損耗、改善熱分布、降低耗損、並可降低輸出電流漣波。次級側搭配使用同步整流技術,提升整體電源轉換器之效率。本文數位控制器使用Microchip公司所推出的dsPIC33FJ16GS502數位信號處理器實現全數位控制,並針對數位控制器設計與開發數位PID補償器及數位濾波器。
    本文分別探討電路操作原理、設計考量、閘極控制訊號設計方法,並實際製作一輸出功率為 (24Vdc/25A)之直流/直流電源轉換器以驗證本文所提出之電路分析與控制方法的正確性與可行性,根據實驗結果顯示所實作具同步整流功能之數位控制全橋相移轉換器,其量測效率最高可達到93.93%。


    In this thesis, a fully-digital phase-shifted full-bridge converter (PSFBC) is developed. The PSFBC has been used widely in medium to high power applications because phase shift control can provide zero voltage switching (ZVS) for primary side switches; therefore achieves high efficiency and high power density. Current doubler rectifier (CDR) with synchronous rectification is adopted in this thesis for secondary side rectification. CDR splits the output current between two filter inductors, which reduces conduction losses, improves thermal distribution, allows for lower profile and possesses the ripple cancellation effect on the output capacitance. Synchronous rectification further increases the conversion efficiency. The digital controller including the digital PID compensator and digital filter is also designed and implemented. In this thesis, the digital controller is implemented using dsPIC33FJ16GS502 digital signal controller (DSC) from Microchip Corp.
    In this thesis, the operating principles, design guidelines and the generation of gating signals are described first. A 600 W (24Vdc/25A) PSFBC prototyping circuit is developed next to validate the correctness of the proposed circuit analysis and control algorithm. According to the experimental results, the peak efficiency of the whole system can achieve 93.93 %.

    摘要I AbstractII 誌謝III 目錄V 圖目錄VII 表目錄X 第一章 緒論1 1.1 研究背景1 1.2 文獻探討2 1.3 研究動機與方法3 1.4 內容大綱5 第二章 次級側整流架構與同步整流技術分析6 2.1 次級側整流架構6 2.1.1 半波整流 (Half-Wave Rectifier)6 2.1.2 中間抽頭整流 (Center Tapped Rectifier)8 2.1.3 全橋整流 (Bridge Type Rectifier)10 2.1.4 電流倍增整流 (Current Doubler Rectifier)12 2.2 同步整流技術分析15 2.2.1 自激式 (Self-Driven)15 2.2.2 它激式 (External-Driven)16 第三章 同步整流全橋相移轉換器硬體架構18 3.1 前言18 3.2 同步整流全橋相移轉換器主架構介紹19 3.2 同步整流全橋相移轉換器控制介紹21 3.2.1 傳統全橋轉換器控制方法21 3.2.2 全橋相移轉換器控制方法21 3.3.3 同步整流全橋相移轉換器控制方法22 3.3.4 回授與功率開關驅動電路25 3.4 同步整流全橋相移轉換器操作模式分析26 3.5 零電壓切換之臨界電流說明與分析40 3.6 有效責任週期分析44 3.7 高頻切換限制45 第四章 硬體電路規格制定與設計49 4.1 制訂電路規格49 4.2 初級側元件設計與選用49 4.2.1 主變壓器設計49 4.2.2 諧振電感設計53 4.2.3 隔離電容設計54 4.2.4 初級側功率開關的選擇55 4.3 次級側元件設計與選用56 4.3.1 輸出倍流電感設計56 4.3.2 輸出濾波電容設計57 4.3.3 次級側同步整流功率開關的選擇58 第五章 同步整流全橋相移轉換器韌體介紹59 5.1 前言59 5.2 dsPIC33FJ16GS502微處理器簡介60 5.3 程式設計流程介紹62 5.4 數位濾波器64 5.4.1 濾波器簡介64 5.4.2 有限與無限脈衝響應濾波器66 5.4.3 有限脈衝響應濾波器設計67 5.4.4 有限脈衝響應數位濾波器驗證72 5.5 數位PID73 5.5.1 數位PID介紹73 5.5.2 PID控制器原理73 5.5.3 數位PID控制器75 第六章 實驗結果與討論78 6.1 實驗波形80 6.2 實測數據91 第七章 結論與未來展望95 7.1 結論95 7.2 未來展望96 參考文獻97

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