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研究生: 莊賀任
Ho-ren Chuang
論文名稱: 基於多核心嵌入式處理器之工業用IC 標誌檢測平台
An Industrial IC Chip Marking Inspection System Based on the Quad-Core Embedded Processor
指導教授: 沈中安
Chung-an Shen
口試委員: 阮聖彰
Shanq-jang Ruan
林淵翔
Yuan-hsiang Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 50
中文關鍵詞: IC標誌檢測圖像偏移機器視覺模板匹配工業控制系統嵌入式系統
外文關鍵詞: IC chip marking inspection, Image offset, Machine vision, Template matching, Industrial control system, Embedded system
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  • 在IC(Integrated Circuit)晶片製作過程中,IC標誌偵測是其中一個重要環節,透過在IC上標誌的檢查,IC擺放方向的正確性可得以確保,並進而保證後續晶片封裝等動作的正確完成。本論文設計並實現第一個基於ARM四核心嵌入式系統平台的IC晶片標誌檢測系統。與之前研究提出的工業電腦(IPC)平台不同,此系統具有低功率消耗、可攜性高、佔據面積小的優勢。此外為了克服嵌入式系統在先天架構上具有運算能力相對較低的缺點,本論文提出了一個新的基於模板匹配的圖像比對演算法以大量減低標誌檢測過程中所需的運算複雜度。與傳統上使用OpenCV函式庫實現的結果相比,此演算法可減少3.29倍的處理時間。再者,為了更進一步增進系統效能,我們基於處理器提供之指令層級平行化架構進行演算法的最佳化並將軟體以多執行緒的方式加以實現。此論文呈現了此演算法原理及最佳化結果,並詳細說明硬體、軟體架構及實作方法。最後我們運用廣泛的實驗結果來證明此IC晶片標誌檢測系統的優點。


    IC (Integrated Circuit) chip marking inspection is one of the critical steps during the IC manufacture process. Through the examination of the marks on the IC chip, the correctness of IC orientation can be assured. In this paper, we present the first design and implementation of an IC chip marking inspection system based on the quad-core embedded ARM processor. Contrary to the previously proposed platforms which are based on the Industrial PCs (IPCs), the proposed system illustrates significant advantages in terms of the low energy consumption, portability, as well as compact occupied space. Moreover, in order to overcome the drawbacks of embedded systems for the relatively lower computational capability, a novel template matching algorithm is proposed to greatly reduce the computational complexity of the process of marking inspection. Compared to the OpenCV implementation, the proposed algorithm reduces the processing time by 3.29×. In addition, instruction-level software parallelism and multithreading methodologies are introduced to further enhance the efficiency of the system. In this paper, the detailed outline of the proposed algorithm is presented and the hardware and software structures and implementations are illustrated. Extensive experiments are also conducted and the results verify the advantages of the proposed IC chip marking inspection system.

    中文摘要 I Abstract II 致謝 IV 目錄 V 圖索引 VII 表索引 IX 第一章 緒論 1 1.1 研究動機與目的 1 1.2 研究背景及文獻探討 2 1.3 論文架構 5 第二章 系統相關背景介紹 6 2.1 演算法介紹 6 2.2 指令層級之平行化 14 2.3 軟體層級之平行化 15 第三章 IC標誌檢測系統 17 3.1 硬體架構 17 3.2 軟體架構 18 3.3 指令層級之最佳化 26 3.4 軟體層級之最佳化 28 第四章 實驗結果與分析 32 4.1 實驗平台及環境 32 4.2 雙模板匹配法與基於NCC的Coarse-to-fine演算法之比較 33 4.3 指令層級最佳化的效能增益 37 4.4 軟體層級最佳化的效能增益 38 4.5 兩種多執行緒的方法比較 40 4.6 完整系統效能 42 4.7 實際辨識結果與圖形化使用者介面設計 43 第五章 結論與未來展望 46 參考文獻 47

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