邊緣應用之門控循環單元網路之積體電路設計與驗證｜國立臺灣科技大學博碩士論文系統

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研究生：	林亭汝 Ting-Ju Lin
論文名稱：	邊緣應用之門控循環單元網路之積體電路設計與驗證 Integrated Circuit Design And Verification of A Gated Recurrent Unit Network for Edge Applications
指導教授：	彭盛裕 Sheng-Yu Peng
口試委員:	吳安宇 An-Yeu Wu 陳新 Hsin Chen 謝易錚 Yi-Zeng Hsieh
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	89
中文關鍵詞：	機器學習硬體、類比門控循環單元神經網路、邊緣運算、硬體友善演算法、軟硬體共同設計
外文關鍵詞：	machine learning (ML) hardware, analog GRU, edge computing, hardware-friendly algorithm, software and hardware co-design
相關次數：	點閱：264 下載：0
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Abstract in Chinese . . . . . . . . . . . . . . . . . . . . vi
Abstract in English . . . . . . . . . . . . . . . . . . . . vii
Acknowledgements . . . . . . . . .. . . . . . . . . . . . . viii
Contents . . . . . . . . . . . . . .. . . . . . . . . . . . ix
List of Figures . . . . . . . . . . . . . . . . . . . . . . xii
List of Tables . . . . . . . . . . .. . . . . . . . . . . . xvii
Introduction . . . . . . . . . . .. . . . . . . . . . . . 1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Background Knowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 Edge Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Gated Recurrent Unit Neural Network . . . . . . . . . . . . . . . . . . . 10
Analog Gated Recurrent Unit Neural Network Circuit and System . . . . . . . 14
1 System-Level Design With Proposed Analog Gated Recurrent Unit Neural
Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1 Hardware-Friendly Software Model . . . . . . . . . . . . . . . . 14
1.2 Training Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 Applied in Classification Problem . . . . . . . . . . . . . . . . . 23
2 Proposed Analog Gated Recurrent Unit Neural Network Architecture . . 25
2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Feature Extraction . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 SRAM-Based Reconfigurable Cognitive Computation Matrix (RCCM) 29
2.4 Activation Function . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5 Memory State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6 Common Gate Normalization . . . . . . . . . . . . . . . . . . . 41
3 Co-Design Between Software and Hardware . . . . . . . . . . . . . . . . 43
3.1 Adjusted Analog Gated Recurrent Unit Neural Network Model . . 44
3.2 Simulation Results Applied to Spike Detection . . . . . . . . . . 49
4 Measurement Result and Comparison . . . . . . . . . . . . . . . . . . . 54
4.1 Feature Extraction Measurement Result . . . . . . . . . . . . . . 55
4.2 Activation Functions Measurement Result . . . . . . . . . . . . . 56
4.3 Memory State Measurement Result . . . . . . . . . . . . . . . . 58
4.4 On-Off Keying Measurement Result . . . . . . . . . . . . . . . . 61
4.5 Voice Activity Detection Measurement Result . . . . . . . . . . . 64
5 Comparison Table . . . . . . . . . . . . . .  . . . . . . . . . . . . . 66
Conclusion and Contribution . . . . . . . . .  . . . . . . . . . . . . . 68
1 Conclusion . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 68
2 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
References . . . . . . . . . . . .. . . . . . . . . . . . . . . 71
                                

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全文公開日期 2033/07/06 (校內網路)
全文公開日期 2121/07/06 (校外網路)
全文公開日期 2121/07/06 (國家圖書館：臺灣博碩士論文系統)

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