本論文中實現一個應用於5G邊緣運算網路封包轉換系統，封包轉換系統(Protocol Conversion Engine)是幫助OpenFlow Switch解析5G行動網路中的GTP(GPRS Tunneling Protocol)封包，使得現今的商用OpenFlow Switch可以在5G行動網路中使用。
封包轉換系統(Protocol Conversion Engine)的架構分成P4語言開發與硬體電路設計兩部份，我們採用P4(Programming Protocol-Independent Packet Processors)一種新興的特定領域開發語言開發Protocol Conversion Engine的封包處理器。使用P4語言開發，我們可以快速開發地Protocol Conversion Engine並且可以在虛擬網路拓樸中驗證。
接著本論文透過Xilinx SDNet將Protocol Conversion Engine的封包處理器實現到FPGA開發平台；再藉由硬體電路設計完成Protocol Conversion Engine封包處理器的硬體架構。
最後，實驗結果顯示Protocol Conversion Engine可以達到40Gbps(4個10Gbps接口)的吞吐量(throughput)、封包處理延遲在5微秒以下、封包遺失率(Packet loss rate)低於網路設備的規範，並且可以透過頻內配置(In-Band Configuration)的方式更新Protocol Conversion Engine。

This paper proposes a Protocol Conversion Engine for Mobile Edge Computing in 5G Networks. The Protocol Conversion Engine support OpenFlow switch to parse GTP (GPRS Tunneling Protocol) packet and OpenFlow Switch can be used on the 5G mobile networks.
The protocol Conversion Engine architecture is divided into two parts: P4 language development and hardware circuit design. We use P4 (Programming Protocol-Independent Packet Processors) that is a new domain-specific language to design protocol Conversion Engine. When we use p4 language to develop protocol Conversion Engine, we can develop quickly and verify in the virtual network topology.
Then this paper implements the packet conversion processor's packet processor to the FPGA development platform through Xilinx SDNet Compiler and the remaining hardware architecture of the Protocol Conversion Engine packet processor is completed by hardware circuit design.
Finally, the experimental results show that the Protocol Conversion Engine’s throughput can reach 40Gbps (4x10Gbps) and packet processing latency is less than 5 us and packet loss rate is less than the standard of internet device. The Protocol Conversion Engine can support In-Band Configuration that is used to update the Protocol Conversion Engine.

[1] I. T. Union, “Recommendation ITU-R M.2083-0,” 2015.
[2] Huang, Anta Nikaein, Navid Stenbock, Tore Ksentini, Adlen Bonnet, Christian, “Low latency MEC framework for SDN-based LTE/LTE-A networks,” IEEE International Conference on Communications, pp. 1-6, 2017.
[3] Zhang, Yang and Niyato, Dusit and Wang, Ping, “Offloading in mobile cloudlet systems with intermittent connectivity,” IEEE Transactions on Mobile Computing, 2015.
[4] Lange, Stanislav and Nguyen-Ngoc, Anh and Gebert, Steffen and Zinner, Thomas and Jarschel, Michael and K{\"o}psel, Andreas and Sune, Marc and Raumer, Daniel and Gallenm{\"u}ller, Sebastian and Carle, Georg and others, “Performance benchmarking of a software-based LTE SGW,” CNSM, 2015.
[5] Amin, Rashid and Reisslein, Martin and Shah, Nadir, “Hybrid SDN networks: A survey of existing approaches,” IEEE Communications Surveys & Tutorials, pp. 3259--3306, 2018.
[6] Zaidi, Zainab and Friderikos, Vasilis and Yousaf, Zarrar and Fletcher, Simon and Dohler, Mischa and Aghvami, Hamid, “Will SDN be part of 5G?,” IEEE Communications Surveys & Tutorials, pp. 3220--3258, 2018.
[7] Gharbaoui, M and Contoli, C and Davoli, G and Cuffaro, G and Martini, B and Paganelli, F and Cerroni, W and Cappanera, P and Castoldi, P, “Demonstration of Latency-Aware and Self-Adaptive Service Chaining in 5G/SDN/NFV infrastructures,” 2018 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN), 2018.
[8] Ma, Lu and Wen, Xiangming and Wang, Luhan and Lu, Zhaoming and Knopp, Raymond, “An SDN/NFV based framework for management and deployment of service based 5G core network,” IEEE China Communications, pp. 86--98, 2018.
[9] Liu, Jiajia and Shi, Yongpeng and Zhao, Lei and Cao, Yurui and Sun, Wen and Kato, Nei, “Joint placement of controllers and gateways in SDN-enabled 5G-satellite integrated network,” IEEE Journal on Selected Areas in Communications, pp. 221--232, 2018.
[10] Hu, Yun Chao and Patel, Milan and Sabella, Dario and Sprecher, Nurit and Young, Valerie, “Mobile edge computing—A key technology towards 5G,” ETSI white paper, pp. 1-16, 2015.
[11] Wei, Xiaojuan and Wang, Shangguang and Zhou, Ao and Xu, Jinliang and Su, Sen and Kumar, Sathish and Yang, Fangchun, “MVR: An architecture for computation offloading in mobile edge computing,” 2017 IEEE International Conference on Edge Computing (EDGE), pp. 232--235, 2017.
[12] Li, Yuanzhe and Wang, Shangguang, “An energy-aware edge server placement algorithm in mobile edge computing,” 2018 IEEE International Conference on Edge Computing (EDGE), pp. 66--73, 2018.
[13] Bosshart, Pat and Daly, Dan and Gibb, Glen and Izzard, Martin and McKeown, Nick and Rexford, Jennifer and Schlesinger, Cole and Talayco, Dan and Vahdat, Amin and Varghese, George and others, “P4: Programming protocol-independent packet processors,” ACM SIGCOMM Computer Communication Review, pp. 87--95, 2014.
[14] Katta, Naga and Hira, Mukesh and Kim, Changhoon and Sivaraman, Anirudh and Rexford, Jennifer, “Hula: Scalable load balancing using programmable data planes,” Proceedings of the Symposium on SDN Research,ACM, p. 10, 2016.
[15] Benet, Cristian Hernandez and Kassler, Andreas J and Benson, Theophilus and Pongracz, Gergely, “MP-HULA: Multipath transport aware load balancing using programmable data planes,” Proceedings of the 2018 Morning Workshop on In-Network Computing,ACM, pp. 7--13, 2018.
[16] Ricart-Sanchez, Ruben and Malagon, Pedro and Salva-Garcia, Pablo and Perez, Enrique Chirivella and Wang, Qi and Calero, Jose M Alcaraz, “Towards an FPGA-Accelerated programmable data path for edge-to-core communications in 5G networks,” Journal of Network and Computer Applications, pp. 80--93, 2018.
[17] Stubbe, Henning, “P4 Compiler & Interpreter: A Survey Henning,” Proc. Future Internet (FI) Innov. Internet Technol. Mobile Commun.(IITM), 2017.
[18] Wang, Han and Soul, Robert and Dang, Huynh Tu and Lee, Ki Suh and Shrivastav, Vishal and Foster, Nate and Weatherspoon, Hakim, “P4FPGA: A rapid prototyping framework for P4,” Proceedings of the Symposium on SDN Research,ACM, pp. 122--135, 2017.
[19] Pit-Claudel, Beno{\^\i}t and Desmouceaux, Yoann and Pfister, Pierre and Townsley, Mark and Clausen, Thomas, “Stateless Load-Aware Load Balancing in P4,” 2018 IEEE 26th International Conference on Network Protocols (ICNP), pp. 418--423, 2018.
[20] Yazdinejad, Abbas and Bohlooli, Ali and Jamshidi, Kamal, “P4 to sdnet: Automatic generation of an efficient protocol-independent packet parser on reconfigurable hardware,” 2018 8th International Conference on Computer and Knowledge Engineering (ICCKE), pp. 159--164, 2018.
[21] Ibanez, Stephen and Brebner, Gordon and McKeown, Nick and Zilberman, Noa, “The P4-> NetFPGA Workflow for Line-Rate Packet Processing,” Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,ACM, pp. 1-9, 2019.
[22] Zilberman, Noa and Audzevich, Yury and Covington, G Adam and Moore, Andrew W, “NetFPGA SUME: Toward 100 Gbps as research commodity,” IEEE micro, pp. 32--41, 2014.
[23] “Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit,” Xilinx , [線上]. Available: https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html.
[24] Xilinx, “UG1252 - P4-SDNet User Guide (v2018.2)”.
[25] Xilinx, “10G/25G High Speed Ethernet Subsystem v2.3(PG210),” 2017.