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研究生: 蔡岳恩
Yueh-En Tsai
論文名稱: 極化碼置信度傳播暨神經網路位元翻轉解碼器之硬體設計
The Hardware Design of Belief Propagation With Neural Network Flip for Polar Codes
指導教授: 王煥宗
Huan-Chun Wang
口試委員: 王瑞堂
Jui-Tang Wang
林敬舜
ChingShun Lin
劉建成
Jian-Cheng Liu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 中文
論文頁數: 70
中文關鍵詞: 極化碼極化碼解碼器置信度傳播超大型積體電路
外文關鍵詞: Polar Code, Polar Code Decoder, Belief Propagation, VLSI
相關次數: 點閱:309下載:0
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本論文提出極化碼(Polar code)置信度傳播暨神經網路位元翻轉解碼器,並且使用超大型積體電路(Very Large Scale Integration, VLSI)硬體設計,主要目標為提高置信度傳播(Belief Propagation)的準確率,因此使用置信度傳播解碼器做為演算法的基礎,加入位元翻轉以提高解碼效能。翻轉集的部分利用神經網路(Neural Network)中的多層感知機(Multilayer Perceptron)來取代傳統的關鍵集(Critical Set)選出每筆資料最適合的翻轉位置,同時加入神經網路訓練的 Scaled Min-sumapproximate,在減少 BP 迭代次數的同時維持一定的準確率,進而提高吞吐量。
本論文使用 Python 作為演算法之軟體模擬平台,並且設計硬體架構,與傳統的置信度傳播解碼器相比,可以在效能方面取得優勢。


This paper proposes a Belief Propagation and Neural Network Bit-Flipping
Decoder for Polar codes, using Very Large Scale Integration (VLSI) to hardware design.
The main objective is to enhance the accuracy of Belief Propagation (BP) by
incorporating bit-flipping techniques to improve the decoding performance. The
flipping set is determined using a Multilayer Perceptron instead of the traditional
Critical Set, selecting the most suitable flipping positions for each data instance.
Additionally, the scaled Min-sum approximate, trained by the Neural Network, is
introduced to reduce the number of BP iterations while maintaining a certain level of
accuracy, thereby improving the throughput.
Python is used as the software simulation platform for algorithm development in
this paper. Furthermore, a hardware architecture is designed to demonstrate the
advantages over traditional Belief Propagation decoders in terms of performance.

圖目錄 v 表目錄 vii 第一章 緒論 1 1.1 研究背景 1 1.2 研究目的 2 1.3 論文架構 2 第二章 極化碼 3 2.1 極化碼介紹 3 2.1.1 B-DMC介紹 3 2.2通道極化 4 2.2.1 通道組合 4 2.2.2 通道分裂 8 2.3 通道極化程度選擇 8 2.4 極化碼編碼 9 2.5 置信度傳播解碼器 10 2.5.1 置信度傳播解碼方式 10 2.5.2 解碼單元 12 2.6 置信度傳播位元翻轉解碼器 13 2.7 循環冗餘校驗 13 2.8 CRITICAL SET建立 13 第三章 神經網路介紹與演算法改良 16 3.1 神經網路 16 3.1.1 神經網路訓練 18 3.2 循環神經網路 19 3.3 演算法改良 20 3.3.1 神經網路訓練翻轉集 21 3.3.2 神經網路參數及訓練資料 22 3.4 總結 24 第四章 演算法程式模擬與驗證 25 4.1 模擬環境設定 25 4.1.2 AWGN通道設定 26 4.2 置信度傳播暨神經網路位元翻轉解碼流程 28 4.3 置信度傳播暨神經網路位元翻轉解碼效能模擬 30 圖目錄 v 表目錄 vii 第一章 緒論 1 1.1 研究背景 1 1.2 研究目的 2 1.3 論文架構 2 第二章 極化碼 3 2.1 極化碼介紹 3 2.1.1 B-DMC介紹 3 2.2通道極化 4 2.2.1 通道組合 4 2.2.2 通道分裂 8 2.3 通道極化程度選擇 8 2.4 極化碼編碼 9 2.5 置信度傳播解碼器 10 2.5.1 置信度傳播解碼方式 10 2.5.2 解碼單元 12 2.6 置信度傳播位元翻轉解碼器 13 2.7 循環冗餘校驗 13 2.8 CRITICAL SET建立 13 第三章 神經網路介紹與演算法改良 16 3.1 神經網路 16 3.1.1 神經網路訓練 18 3.2 循環神經網路 19 3.3 演算法改良 20 3.3.1 神經網路訓練翻轉集 21 3.3.2 神經網路參數及訓練資料 22 3.4 總結 24 第四章 演算法程式模擬與驗證 25 4.1 模擬環境設定 25 4.1.2 AWGN通道設定 26 4.2 置信度傳播暨神經網路位元翻轉解碼流程 28 4.3 置信度傳播暨神經網路位元翻轉解碼效能模擬 30 第五章 硬體架構 39 5.1 電路方塊圖 39 5.1.1 BP Decoder 40 5.1.2 Process Element(PE) 41 5.1.3 神經網路 (NN) 43 5.1.4 排序電路 44 5.1.5 CRC 45 第六章 晶片設計流程與參數選擇 47 6.1 晶片設計流程 47 6.2 I/O PAD的選擇 50 6.3 文獻比較 52 第七章 結論與未來展望 56 參考文獻 57 附錄一 中英名稱對照表 61

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