本論文描述一個聲頻應用之二加一階混和強健式多級串接三角積分調變器，使用標準0.18μm互補式金氧半導體製程。和傳統的強健式多級串接三角積分調變器相比，本篇論文提出之混和式強健式多級串接三角積分調變器同時使用了反向積分器與非反向積分器來達到將第一級量化雜訊消除的功能，所以可以提供多3-dB的訊號-量化雜訊比。在第一級與第二級中間插入了被動低通濾波器來壓抑頻寬外的量化雜訊，而不是透過調整係數來穩定系統。同時，採用輸入前饋路徑與有限脈衝響應回授來提升線性度和降低轉導放大器對迴轉率的需求。
此晶片採用TSMC 0.18μm 1P6M的互補金氧半導體製程來實現。在1.8伏特的供應電壓下，取樣頻率為6.144百萬赫(MHz)。訊號頻寬為聲頻應用之24千赫(kHz)與128倍超取樣率。此調變器可達到峰值92.39 dB的信號雜訊及失真比，具有15.06位元等效解析度，94.73 dB信號雜訊比與 95.56 dB動態範圍。在這樣的結果下得到的FoM為699 fJ/conversion-step與168.8dB。消耗功率為1146 μW.

This thesis presents a Hybrid Sturdy MASH-21(HSMASH-21) Delta-Sigma Modulator (DSM) for audio applications using standard 0.18μm CMOS technology. Compare with the conventional Sturdy-MASH architecture, the HSMASH-21 DSM employs inverting and non-inverting switched capacitor integrators to eliminate the first-stage quantization noise, resulting in a 3-dB SQNR improvement. The passive low pass filter is inserted between the first and the second integrator to suppress the out-of-band quantization noise, instead of adjusting coefficients to stabilize the system. Meanwhile, an input feedforward path and the FIR DACs are employed to improve linearity and reduce the slew rate requirement of the OTA.
This DSM chip was implemented in TSMC 0.18μm CMOS process. Operated at 1.8V supply voltage with a 6.144 MHz sampling rate, the proposed HSMASH-21 DSM is designed to work with a bandwidth of 24 kHz for audio applications. Thus, the OSR is 128. The proposed modulator achieves a 92.39 dB peak SNDR, which is equivalent to possessing 15.06 effective number of bits (ENOB). It also achieves a 94.73 dB SNR, and a 95.56 dB dynamic range (DR). Two popular Figure-of-Merits (FoMs) are 699 fJ/conversion-step and 168.8 dB, respectively. The power consumption of the DSM chip is 1146 μW.

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