簡易檢索 / 詳目顯示

研究生: 賴承謙
CHENG-QIAN LAI
論文名稱: 超低功耗十二位元類比至數位轉換器
Ultra Low Power 12-Bit Analog-to-Digital Converter
指導教授: 陳伯奇
PoKi Chen
鍾勇輝
Yung-Hui Chung
口試委員: 鄭桂忠
Kea-Tiong Tang
徐浩桓
Hao-Huan Hsu
陳伯奇
Po-Ki Chen
鍾勇輝
Yung-Hui Chung
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 87
中文關鍵詞: 低功耗類比至數位轉換器連續漸近式類比至數位轉換器電容式數位至類比轉換器
外文關鍵詞: Low power, Analog-to-Digital Converter, Successive Approximation Register Analog-to-Digital Converter, Capacitive Digital-to-Analog Converter
相關次數: 點閱:224下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

  • 摘 要 i ABSTRACT ii 誌 謝 iii 目 錄 iv 圖目錄 vi 表目錄 ix 第1章 緒論 1 1.1 研究動機 1 1.2 論文架構 2 第2章 類比至數位轉換器介紹 3 2.1 類比至數位轉換器效能之衡量標準 4 2.1.1 取樣速率 4 2.1.2 解析度 4 2.1.3 偏移誤差與增益誤差 4 2.1.4 非線性誤差 5 2.1.5 量化雜訊 6 2.1.6 訊號雜訊比 8 2.1.7 訊號對雜訊與諧波比 8 2.1.8 無雜散動態範圍 9 2.1.9 有效位元數 9 2.1.10 價值指標 9 2.2 類比至數位轉換器選擇 10 第3章 電路設計 11 3.1 追蹤保持電路 16 3.1.1 單一電晶體開關 17 3.1.2 互補式開關 19 3.1.3 靴帶式取樣開關 21 3.1.4 兩倍電壓靴帶式取樣開關 28 3.1.5 保持模式漏電流 31 3.1.6 電壓幫浦式時脈驅動電路 34 3.2 比較器 37 3.2.1 動態比較器 37 3.2.2 比較器雜訊模擬 40 3.3 連續漸近式控制電路 43 3.3.1 同步與非同步式控制電路 43 3.3.2 同步式連續漸近控制電路 44 3.3.3 單位元連續漸近控制電路 46 3.3.4 開關控制電路 55 第4章 電路模擬與佈局 57 4.1 晶片佈局 57 4.2 佈局前模擬 58 4.3 佈局後模擬 64 4.4 效能比較表 70 第5章 結論與未來展望 71 5.1 結論 71 5.2 未來展望 72 參考文獻 73

    [1] Y. Ji, C. Jeon, H. Son, B. Kim, H. Park and J. Sim, "5.8 A 9.3nW all-in-one
    bandgap voltage and current reference circuit," 2017 IEEE International
    Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 100-101.
    [2] J. M. Lee et al., "5.7 A 29nW bandgap reference circuit," 2015 IEEE
    International Solid-State Circuits Conference - (ISSCC) Digest of Technical
    Papers, San Francisco, CA, 2015, pp. 1-3.
    [3] R. Van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog
    Converters. Kluwer Academic Publishers, second ed., 2003.
    [4] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, second
    ed., 2001.
    [5] Y. Zhu et al., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,"
    in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010.
    [6] B. Razavi, Principles of Data Conversion System Design. John Willy and Sons,
    Inc., first ed., 1995.
    [7] M. Dessouky and A. Kaiser, "Input switch configuration suitable for rail-to-rail
    operation of switched op amp circuits," in Electronics Letters, vol. 35, no. 1, pp.
    8-10, 7 Jan. 1999.
    [8] C. C. Enz, F. Krummenacher, E. A. Vittoz, "An analytical MOS transistor model
    valid in all regions of operation and dedicated to low-voltage and low-current
    applications", Analog Integrat. Circuits Signal Process., vol. 8, pp. 83-114, 1995.
    [9] J. Lin and C. Hsieh, "A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm
    CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.
    64, no. 3, pp. 562-572, March 2017.
    [10] S. He and C. E. Saavedra, "Design of a Low-Voltage and Low-Distortion Mixer
    Through Volterra-Series Analysis," in IEEE Transactions on Microwave Theory
    and Techniques, vol. 61, no. 1, pp. 177-184, Jan. 2013.
    [11] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford University
    Press, second ed. 2002.
    [12] A. Nikoozadeh and B. Murmann, "An Analysis of Latch Comparator Offset Due
    to Load Capacitor Mismatch," in IEEE Transactions on Circuits and Systems II:
    Express Briefs, vol. 53, no. 12, pp. 1398-1402, Dec. 2006.
    [13] Y. Chung and M. Chiang, "A 12-Bit Synchronous-SAR ADC for IoT
    Applications," 2019 IEEE International Symposium on Circuits and Systems
    (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
    [14] C. Liu, S. Chang, G. Huang and Y. Lin, "A 10-bit 50-MS/s SAR ADC With a
    Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State
    Circuits, vol. 45, no. 4, pp. 731-740, April 2010.
    [15] D. Zhang, A. Bhide and A. Alvandpour, "A 53-nW 9.1-ENOB 1-kS/s SAR ADC
    in 0.13- μm CMOS for Medical Implant Devices," in IEEE Journal of
    Solid-State Circuits, vol. 47, no. 7, pp. 1585-1593, July 2012.
    [16] Z. Zhu and Y. Liang, "A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-μm
    CMOS for Medical Implant Devices," in IEEE Transactions on Circuits and
    Systems I: Regular Papers, vol. 62, no. 9, pp. 2167-2176, Sept. 2015.
    [17] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE
    J.Solid-State Circuits, vol. 24, no. 1, Feb. 1989, pp. 62-70.
    [18] P. Harpe, H. Gao, R. van Dommele, E. Cantatore and A. van Roermund, "21.2 A
    3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC," 2015 IEEE International Solid-State Circuits Conference
    - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3.
    [19] W. Mao, Y. Li, C. Heng and Y. Lian, "A Low Power 12-bit 1-kS/s SAR ADC for
    Biomedical Signal Processing," in IEEE Transactions on Circuits and Systems I:
    Regular Papers, vol. 66, no. 2, pp. 477-488, Feb. 2019.
    [20] X. Zou, X. Xu, L. Yao and Y. Lian, "A 1-V 450-nW Fully Integrated
    Programmable Biomedical Sensor Interface Chip," in IEEE Journal of
    Solid-State Circuits, vol. 44, no. 4, pp. 1067-1077, April 2009.

    無法下載圖示 全文公開日期 2024/08/27 (校內網路)
    全文公開日期 2024/08/27 (校外網路)
    全文公開日期 2024/08/27 (國家圖書館:臺灣博碩士論文系統)
    QR CODE