隨著產品需求的演變,元件不斷微縮,通道長度也隨之變小,短通道效應(SCE)引起元件的漏電流增加並使得導通(ION)與截止(IOff)的電流比降低。為了改善短通道效應,我們選用 FINFET 結構,其具有良好的通道控制力,而被廣泛應用。然而,傳統的 FINFET 伴隨著 DIBL 的問題出現,本論文採用具有固定能障之蕭特基源汲極 FINFET 去改善 DIBL 的效應。
本文利用 Synopsys TCAD 模擬軟體去進行數據上的分析,並根據模擬的結果調整元件參數。結果顯示,在低操作電壓時,蕭特基源極搭配n+ 汲極之 FINFET因為沒有 DIBL 的問題,且由於電場變小,減少了帶到帶穿隧效應,所以具有最良好的特性。當鰭片高度為 30 nm,鰭片寬度為 5 nm,在汲極偏壓為 0.6 伏特以及閘極偏壓為 0 伏特時,其總漏電流約為 1.6 nA,此外,在汲極偏壓為 0.6 伏特以及閘極偏壓為 0.6 伏特的情況下,其次臨限擺幅(Subthreshold Swing , S.S.)為 81 mV/dec 而汲極電流(Id)為 39.5 μA,然對應的傳統 FINFET,其次臨限擺幅(Subthreshold Swing , S.S.)為 94 mV/dec 而汲極電流(Id)為 25.1 μA。
此外,對具有蕭特基汲極之蕭特基源極 FINFET 而言,因為它比蕭特基源極搭配n+汲極FINFET 額外地在汲極區域產生電洞穿隧,所以會產生較大的漏電流,在汲極偏壓為 0.6 伏特以及閘極偏壓為 0.6 伏特的情況下,其次臨限擺幅為 95mV/dec 而汲極電流(ID)為 21.5 μA。

As product demands evolve, components are continuously scaled down, resulting
in a reduction in channel length. The short-channel effect (SCE) causes an increase in leakage current and a decrease in the ratio of on-current (ION) to off-current (IOFF) in the device.
In order to improve the short-channel effect, we have chosen the FINFET structure,
which has excellent channel control and is widely used. However, traditional FINFETs
come with the issue of Drain Induced Barrier Lowering (DIBL). This paper adopts the
approach of using a Schottky S/D FINFET with a fixed barrier to improve the DIBL
effect.
This thesis used Synopsys TCAD simulation software to analyze the data and adjust
device parameters, based on the simulation results. The Schottky source with n
+ drain FINFET exhibits the best characteristics at low VD bias due to the absence of DIBL and reduced band-to-band tunneling effects due to the decreased electric field. With a fin height of 30 nm and a fin width of 5 nm, at a drain bias of 0.6 V and a gate bias of 0 V, the total leakage current is approximately 1.6 nA. Additionally, under a drain bias of 0.6 V and a gate bias of 0.6 V, the subthreshold swing (S.S.) is 81 mV/dec and the drain current (ID) is 39.5 μA for the Schottky source FINFET. In contrast, the corresponding values for the conventional FINFET are a subthreshold swing (S.S.) of 94 mV/dec and a drain current (ID) of 25.1 μA.
Furthermore, for the Schottky S/D FINFET, an additional leakage path, compared
to the Schottky source with n+ drain FINFET, is caused and thus a larger leakage current is induced. At a drain bias of 0.6 V and a gate bias of 0.6 V, it exhibits a subthreshold swing of 95 mV/dec and a drain current (ID) of 21.5 μA.

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