基於異質多核心控制系統｜國立臺灣科技大學博碩士論文系統

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研究生：	張孟偉 Meng-Wei Chang
論文名稱：	基於異質多核心控制系統 Based on Heterogeneous Multi-Core Control Systems
指導教授：	蘇順豐 Shun-Feng Su
口試委員:	李祖添蘇順豐莊鎮嘉陳美勇余國瑞陸敬互
學位類別：	博士 Doctor
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	112
語文別：	英文
論文頁數：	131
中文關鍵詞：	異質多核心、控制系統、自適應計算、軟體定義硬體
外文關鍵詞：	Heterogeneous multicore, control system, adaptive computing, software-defined hardware
相關次數：	點閱：47 下載：0
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上一筆

1.異質多核心在控制系統中的應用：
本研究部分利用結合 Cortex A53 和 Cortex M4F 處理器的異質多核心架構開發模糊控制系統。該設計整合了 PREEMPT-RT 和雙核心方法來改進即時任務管理，並採用模型-視圖-控制器 (MVC) 架構來實現更清晰的操作角色分離和增強的系統整合。這種結構化方法提高了工業模糊控制應用的效能和可擴展性，確保高效的任務執行和系統可靠性。
2.計算科學異質多核心系統中的自適應計算：
該研究透過創建神經網路加速單元來探索自適應計算，該單元使用高級綜合（HLS）來實現，以有效地將高級描述轉換為數位電路。此外，它還結合了脈動陣列來形成低功耗、高吞吐量的平行處理單元，促進適合廣泛神經網路運算的快速資料處理。此設定支援可擴展且適應性強的計算電路，滿足科學研究和複雜數據分析不斷增長的需求。
整體影響：
這些研究方向證明了異質多核心系統在處理工業和科學領域複雜計算任務的有效性。先進運算架構和結構化系統設計的整合增強了控制和處理解決方案的適應性和效率，為自動化和運算科學的進步鋪平了道路。

1. Application of Heterogeneous Multicores in Control Systems:
This research segment develops a fuzzy control system utilizing a heterogeneous multicore architecture combining Cortex A53 and Cortex M4F processors. The design integrates PREEMPT-RT and Dual-core approach for improved real-time task management and employs the Model-View-Controller (MVC) architecture for clearer operational role separation and enhanced system integration. This structured approach boosts performance and scalability in industrial fuzzy control applications, ensuring efficient task execution and system reliability.
2. Adaptive Computing in Heterogeneous Multicore Systems for Computational Science:
The study explores adaptive computing by creating a neural network acceleration unit, implemented using High-level Synthesis (HLS) to convert high-level descriptions into digital circuits efficiently. Additionally, it incorporates systolic arrays to form a low-power, high-throughput parallel processing unit, facilitating rapid data processing suitable for extensive neural network computations. This setup supports scalable and adaptable computational circuit, addressing the growing demands of scientific research and complex data analyses.
Overall Impact:
These research directions demonstrate the effectiveness of heterogeneous multicore systems in handling sophisticated computational tasks across industrial and scientific fields. The integration of advanced computational architectures and structured system design enhances the adaptability and efficiency of control and processing solutions, paving the way for advancements in automation and computational sciences.

Table of Contents
中文摘要	I
Abstract	II
致謝	III
Table of Contents	IV
List of Figures	VI
List of Tables	VIII
Chapter 1	Introduction	9
1.1	Background	9
1.2	Traditional and Next-Generation Control Systems	14
1.3	Heterogeneous Multi-Core and Real-Time Capabilities	19
1.4	Motivation	22
1.5	System Overview	24
1.6	Contributions	29
1.7	Thesis Organization	31
Chapter 2	Multi-Core Processors	33
2.1	Homogeneous Multi-Core Processors	35
2.2	Heterogeneous Multi-Core Processors	37
2.3	Communication in Heterogeneous Multi-Core Systems	42
2.4	Heterogeneous Hybrid Computing structure	45
2.4.1 Fuzzy Modelling Porting	49
2.4.2 Fuzzy Modelling	50
2.5	Heterogeneous Hybrid Control Systems	53
Chapter 3	Heterogeneous Multicore Adaptive Chip	58
3.1	Neural network framework – architecture	64
3.1.1 High performance convolution - GEMM/Im2col	66
3.1.2 Matrix multiplication	70
3.2	Systolic arrays are specialized hardware architectures	72
3.3	Soc platform	75
3.3.1 High-level Synthesis	82
3.3.2 High-level synthesis - directive	83
3.4	Adaptive computing / software defined hardware	88
3.5	Adaptive operating system – actions	91
Chapter 4	Adaptive Computing - Neural Network Acceleration Unit	94
4.1	Matrix Acceleration Unit Design Operation Flow	96
4.2	Software-defined system-on-chip (SoC)	99
4.3	Block Data segmentation algorithm	100
Chapter 5	Experiments	102
5.1	Mixed simulation and verification of physical entities	104
5.2	High-level synthesis (HLS) - Systolic arrays	108
5.3	Implementation of neural acceleration unit	110
5.4	Results	112
5.5	Math And Memory Bounds	116
Chapter 6	Conclusion	118
6.1	Conclusion	118
6.2	Future Work	119
References	122

List of Figures
Figure 1 1 Microprocessor and Microprocessor Block Diagram.	15
Figure 1 2 Design flow of AMD/Xilinx Vivado HLS	26
Figure 1 3 Design flow of Xilinx Vivado HLS	27
Figure 2 1 TI AM335x Functional Block Diagram.	37
Figure 2 2 Big.Little heterogeneous multiprocessing.	39
Figure 2 3 Functional Block Diagram of Various Brand.	41
Figure 2 4 RPMsg Communication protocol.	43
Figure 2 5 RPMsg Interrupt Communication.	44
Figure 2 6 Hybrid control Systems - Block diagram.	47
Figure 2 7 Hybrid control Systems – MVC design structure.	48
Figure 2 6 Fuzzy Modelling Porting.	50
Figure 2 7 Fuzzy Mamdani Rule Inference.	52
Figure 2 8 Fuzzy Mamdani Control Surface.	53
Figure 2 9 Based on Smart Cockpit and Fuzzy Control System.	55
Figure 2 10 Fuzzy Control Environment for TI SK-AM62P-LP	56
Figure 3 1 Neural network framework operation.	65
Figure 3 2 GEMM operation.	67
Figure 3 3 Systolic arrays workflow.	73
Figure 3 4 Kria Robotics Stack (KRS).	77
Figure 3 5 Kria KV260 Verification platform Block Diagram.	79
Figure 3 6 Kria KV260 Vision AI Starter Kit.	81
Figure 3 7 Software-defined definition and characteristics.	90
Figure 3 8 Adaptive operating system – actions.	92
Figure 4 1 Software-Defined SoC - Neural Network Acceleration Unit.	95
Figure 4 2 Matrix Acceleration Unit Design Operation Flow.	98
Figure 4 3 Block Data segmentation algorithm.	101
Figure 5 1 Accelerated circuit architecture & data processing.	104
Figure 5 2 The design flow of a IC.	105
Figure 5 3 HLS Algorithm and Acceleration Circuit Flow.	107
Figure 5 4 X86 platform systolic array – int data format.	113
Figure 5 5 X86 platform systolic array – float data format.	114
Figure 5 6 X86 platform systolic array – double data format.	114
Figure 5 7 Xilinx platform systolic array – int 8 format.	115
Figure 5 8 Xilinx platform systolic array – int 16 format.	115
Figure 5 9 Xilinx platform systolic array – int 32 format.	116


List of Tables
Table 1 1 Most Common Control Methods. [1,2,3]	11
Table 1 2 Comparison Fuzzy Control and Neural Network Control.	13
Table 1 3 Microprocessor/ Microcontroller Differences.	16
Table 1 4 The Advantages of Heterogeneous Multi-Core Systems.	18
Table 1 5 Methods for Achieving Real-Time System Response	21
Table 2 1 Homogeneous / Heterogeneous Multi-Core Processors.	35
Table 2 2 Fuzzy Modelling membership functions.	52
Table 2 3 Power Consumption in Different System States.	57
Table 3 1 Adaptive and traditional chip comparison.	59
Table 3 2 Adaptive and traditional chip comparison.	61
Table 3 3 Kria KV260 Vision AI Starter Kit Product Details.	81
Table 3 4 Optimizing for Latency.	86
Table 3 5 Optimizing for Area.	87
Table 5 3 Synthesis Circuit and Analog Server Specifications	107
Table 5 1 Hardware cost analysis different programming languages.	109
Table 5 2 Software-defined SoC - neural network acceleration unit.	111
                                

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全文公開日期 2034/05/02 (校內網路)
全文公開日期 2034/05/02 (校外網路)
全文公開日期 2034/05/02 (國家圖書館：臺灣博碩士論文系統)

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