傳統上為了加快全數位式鎖相迴路的鎖定速度，通常使用時間數位轉換器，在訊號剛輸入的前幾個週期中先計算出一粗略的值，控制震盪器輸出於相近的頻率，以增快鎖定速度。本論文則提供一個新的數位控制震盪器的架構，使得全數位式鎖相迴路不用加上時間數位轉換器，也能加快鎖定時間。此外，本論文提出一個簡單的內部自我量測時脈抖動的電路，以測量phase jitter與peak-to-peak jitter兩種時脈抖動。此電路的設計概念相當簡單，係以cell-based library 提供的數位邏輯閘，配合簡單的游標尺法與脈波縮減概念完成。
完成的晶片已經以TSMC 0.18 m CMOS 1P4M cell-based製程下線，核心面積330 m × 345 m，整體面積為1300 m × 1300 m，鎖相迴路鎖定範圍為70-495 MHz。時脈抖動量測電路解析度約為20 ps，phase jitter可量測的範圍約200 ps，可量peak-to-peak jitter的信號週期範圍為2 ns-50 ns。當操作頻率在100 MHz時，鎖相迴路與量測電路消耗功率為23.4 mW。

The time-to-digital converter (TDC) is widely used in ADPLL to speed up the locking time. The rationale behind this is to calculate a roughly control value so as to make the digital controlled oscillator (DCO) oscillate at a frequency near the input frequency. In this thesis, we propose a new DCO that has a faster locking time but does not need the use of TDC. In addition, in the thesis we present a built-in self-test (BIST) circuit for measuring two kinds of time jitter: phase jitter and peak-to-peak jitter. The design idea of the circuit is based on the techniques of vernier delay line (VDL) and pulse shrinking accompanying the gates from a cell-based design kit.
The resulting chip has been implemented by TSMC 0.18-μm CMOS cell-based design kit. The core area is 330 m × 345 m and the total area (with bounding PAD) is 1300 m × 1300 m. The measured results are as follows. The locking range of PLL is 70 MHz to 495 MHz; the resolution of BIST time jitter circuit is about 20 ps; the capture range of phase jitter is about ±200 ps; the capture range of peak-to-peak jitter is 2 ns to 50 ns. The power dissipation is 23.4 mW at the operating frequency of 100 MHz.

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