嵌入式系統具備著體積小、耗電低的優勢，但也導致硬體資源相當稀缺。隨著科技的日新月異，越來越多演算法被提出，並且這些演算法也會需要更多的硬體資源來進行運算。因此，搭載了多個硬體運算資源的異質性嵌入式系統及平台成為了一大重點。對於異質性嵌入式系統而言，能夠有效運用系統上的硬體資源，將成為一大關鍵。本文針對異質性嵌入式系統提出了一個高效率演算法架構，能夠大幅減少硬體閒置時間，並且確保演算法運算時會完整運用到硬體資源。基於此架構，本文針對兩種不同的演算法進行重新設計，並且能夠讓這兩種演算法只需要原先的42.8%以及64.1%的運算時間即可完成相同的運算內容。

Embedded systems have the advantages of small size and low power consumption, but they also suffer from limited hardware resources. With the rapid advancement of technology, an increasing number of algorithms are being proposed, and these algorithms require more hardware resources for computation. Therefore, heterogeneous embedded systems and platforms with multiple hardware computational resources have become a major focus. For heterogeneous embedded systems, the effective utilization of hardware resources on the system becomes a key factor. In this paper, we propose an efficient algorithm architecture for heterogeneous embedded systems, which significantly reduces hardware idle time and ensures the complete utilization of hardware resources during algorithm execution. Based on proposed architecture, we redesign two different algorithms, which can achieve the same computational tasks in only 42.8% and 64.1% of the original computation time, respectively.

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