研究生: |
沙中霖 Chung-Lin Sha |
---|---|
論文名稱: |
基於 Expanding Subexpression Space 之整係數 FIR 濾波器設計與實現 Fixed-point FIR Filter Design and Implementation in the Expanding Subexpression Space |
指導教授: |
姚嘉瑜
Chia-Yu Yao |
口試委員: |
許新添
Hsin-Teng Hsu 簡江儒 Chiang-Ju Chien 王乃堅 Nai-Jian Wang |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 英文 |
論文頁數: | 98 |
中文關鍵詞: | FIR濾波器 、HDL程式產生器 、Common Subexpression Elimination (CSE) 、定點式係數 、線性規劃 、Expanding Subexpression Space |
外文關鍵詞: | FIR Filter, HDL Code Generator, Common Subexpression Elimination (CSE), fix-point coefficient, linear programming, Expanding Subexpression Space |
相關次數: | 點閱:261 下載:7 |
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本論文提出了一個整合整係數濾波器的設計與實現於一個設計流程的方法。本論文所提出的方法是在 expanding subexpression space 的架構下設計整係數濾波器的係數,在濾波器設計的同時,也同時評估硬體實現的複雜度,並回授到演算法內讓演算法可以根據硬體的複雜度反覆的重新設計濾波器係數。論文中的例子顯示出我們可以得到比之前其他研究結果較低的硬體複雜度。此外本論文亦提供自動將濾波器實現轉換成 Verilog 或 VHDL 程式碼的 HDL 產生器,並與Matlab 之 fdatool 產生的 HDL 程式碼性能做比較。
This thesis presents a method of combining the design and the implementation of fixed-point FIR filters into one design flow. The proposed method designs the fixed-point coefficients in an expanding subexpression space. During the design process, the implementation cost is estimated as well and the cost is fed back to the design routine such that the algorithm can redesign the fixed-point coefficients iteratively. Design examples show that we can obtain better hardware-cost-effective FIR filters than the results reported by other researchers. This thesis also contributes an HDL generator of FIR filters designed by the proposed method. It can generate Verilog or VHDL code of the FIR filter. Comparison of the HDL code performance with the code designed by Matlab’s fdatool is also given in this thesis.
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