現今IC半導體朝向單元件多運算功能整合之趨勢，需要高I/O密度，及更輕薄的封裝尺寸以達到摩爾定律，甚至超越摩爾定律的成長速度。電晶體的密度需求不斷的以倍數增加，也伴隨而來在製程上面對更多新的挑戰及新問題需要克服，例如在晶圓製程上由於電晶體間節點距離的靠近，產生電子電荷的堆積造成信號異常，或相鄰電路間的相互干擾，特別是當工作時脈增加時，其影響更為顯著。因此，在晶圓的製造技術，例如在90nm或更低的節點技術，使用更低的介電係數的介電材料來改善其阻絕特性是必要的。低介電係數的阻絕材料在實務上大多以多孔性材質來達成，其物理特性亦相較於一般之二氧化矽更為易脆，且金屬層間黏著力下降，機械強度降低，相較於過去的晶圓切單加工，更容易造成晶片崩缺，晶片崩裂，金屬層脫離等問題。因此發展出以增加雷射開槽加工的方式，在以鑽石刀切單前，移除在晶圓切割道上表層的金屬及低價電係數(Low-k) 的二氧化矽以降低切單時可能造成之破壞。本篇論文運用不同的雷射開槽及鑽石刀下刀參數進行實驗，以改善低價電常數晶圓切單時的晶片崩裂問題，並分別以光學顯微鏡、掃描式電子顯微鏡，及FIB進行檢測，同時驗證非破壞性紅外線光學顯微鏡之可靠性。 最後將實驗所得之最佳切單參數進行25片low-k晶圓之切單實驗並以紅外線光學顯微鏡進行檢驗，結果顯示本研究所提出之切單參數可有效消除low-k晶圓切單時的側向崩缺，提升產品良率及IC構裝之可靠度。

The trend of semiconductor IC packaging demanding for higher I/O density with smaller and thinner chip scale or package form factor in order to keep up with Moore’s Law. The increase of transistor density introduces performance challenges such as electron charge build-up or cross-talk when increasing processing speed. It’s a mandatory when wafer fabrication node size downscaling to 90nm or below, Low-k dielectrics material is required in order to enhance the dielectric property, the Low-k dielectric materials are typically porosity with weaker adhesion and lower mechanical strength which have a tendency to chip, crack and edge peel with traditional mechanical dicing method. Laser grooving process is developed to remove Low-k material prior to dicing saw to avoid such mechanical damage. Experimental study was conducted in this thesis on various critical parameters of laser grooving and blade-dicing to improve low-k wafer die cracking problem. Failure modes were analyzed using optical microscope, IR scope, SEM(Scanning Electron Microscopy) and FIB(Focus-Ion Beam). The study result concluded a preventative solution for die-cracking problem and enhanced IC packaging yield and reliability.

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