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研究生： 陳福文
Fu-Wen Chen
論文名稱： 堆疊式寬除頻範圍除4及低功耗注入鎖定除2除3除頻器之設計
Design of A Wide-Locking Range Divide-By-4 Using Stack and Low Power Injection-Locked Frequency Divide-By-2/3
指導教授： 張勝良
Sheng-Lyang Jang
林士駿
Shih-Chun Lin
口試委員: 徐敬文
Ching-Wen Hsue
徐世祥
Shih-Hsiang Hsu
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 134
中文關鍵詞： 注入鎖定除頻器
外文關鍵詞： Injection-Locked Frequency Divider
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  •  上一筆

    • 第一部分，呈現是使用一個電容性交叉耦合的注入鎖定除二除頻器，實現於台積電(TSMC)點一八製程，晶片面積為0.550 × 1.027 mm2，此架構由兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器，以及一個用來注入訊號的N型金氧半電晶體並聯共振腔一個電感所組成。除二除頻器，在供應電壓為0.7伏特時，功耗為5.66毫瓦，當注入功率為0 dBm時，除頻範圍可從3.1 GHz至10.6 GHz，共7.5 GHz，百分比為109.5%。
    第二部份，呈現是使用一個電容性交叉耦合的注入鎖定除三除頻器，實現於台積電(TSMC) SiGe18製程中，晶片面積為0.884 × 0.645 mm2，此架構是由兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器，以及一組差動用來注入訊號的N型金氧半電晶體並聯共振腔三個電感所組成。此除三除頻器，在供應電壓為1.09伏特時，消耗功率為6.4毫瓦，當注入功率為0 dBm時，除頻範圍從5.05 GHz到10.43 GHz，共5.38 GHz，百分比為69.5%。
    第三部分，呈現是使用一個電容性交叉耦合的注入鎖定除二除頻器，此架構由兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器，以及一個用來注入訊號的N型金氧半電晶體並聯共振腔三個電感所組成，此架構使提升基板電壓降低臨界電壓，達成低功耗效果，實現於台積電(TSMC)點一八製程，晶片面積為0.978×0.797 mm2，此除二除頻器，在供應電壓為0.6伏特時，所消耗的功率為2.208毫瓦，當注入功率為0 dBm時，除頻範圍從3.5 GHz至7.1 GHz，百分比為67.92%。
    第四部分，呈現是使用Current Reused注入鎖定除頻器，此架構使用互補式NP型金氧半電晶體交錯耦合對為中心所組成的電壓控制震盪器，以及兩個用來注入訊號的N型金氧半電晶體，此除四除頻器架構概念，是利用一組除頻器工作後，將輸出訊號拉至下一級除頻器，有效提升除頻範圍，此除頻器實現於台積電(TSMC)點一八製程，晶片面積為0.644 × 0.908 mm2，在供應電壓為1.6伏特時，所需功率消耗為9.93毫瓦，當注入功率為0 dBm時，除頻範圍可從11.4 GHz至17.1 GHz，共5.7 GHz，百分比為40%，當注入功率為1 dBm時，除頻範圍可從11.2 GHz至17.3 GHz，共6.1 GHz，百分比為42.8%。

    First, this thesis presents a wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a differential VCO with one injection MOSFET for coupling the external signal to the resonator and uses a center-tapped inductor and parasitic capacitor to form the resonator. At the supply voltage of 0.7 V, the divider’s free-running frequency is 3.32 GHz, and at the incident power of 0 dBm the locking range is about 7.5 GHz (109.5%), from the incident frequency 3.1 to 10.6 GHz. The input sensitivity plot shows over-lapped locking range characteristics. The core power consumption is 5.66 mW. The die area is 0.550 ×1.027 mm2.
    Second, this thesis presents a low power and wide locking range divide-by-3 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm SiGe BiCMOS process. The ILFD is based on a differential VCO with dual injection MOSFETs for coupling the external signal to the resonator. The power consumption of the ILFD core is 6.4 mW and the locking range is from 5.38 GHz (69.5%) from 5.05 to 10.43 GHz at injection power Pinj = 0 dBm. At the supply voltage of 1.09 V, the divider’s free-running frequency is 2.47 GHz. The die area is 0.884 × 0.645 mm2.
    Third, this thesis presents a lower power and wide locking range divide-by-2 with capacitive cross-coupled injection-locked frequency divider (ILFD) implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a differential VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses body-biased capacitive cross-coupled oscillator for low voltage operation and low power. At the supply voltage of 0.6 V, the divider’s free-running frequency is 2.893 GHz, and at the incident power of 0 dBm the locking range is about 3.6 GHz (67.92％) from 3.5 to 7.1 GHz. The core power consumption is 2.208mW. The die area is 0.978 × 0.797 mm2.
    Forth, a current-reused LC divide-by-4 injection-locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18 μm 1P6M CMOS process. The proposed ILFD is based on a p-core cross-coupled voltage-controlled oscillator (VCO) stacked on a n-core cross-coupled VCO. Conventional harmonic mixer divide-by-4 ILFD has limited locking range, and this thesis shows a wide locking range divide-by-4 ILFD designed with linear mixer technique. At the drain-source bias of 1.6 V and at the incident power of 0 dBm, the locking range is 5.7 GHz (40%) from 11.4 to 17.1 GHz, when the incident power of 2 dBm, the locking range is 6.1 GHz (42.8%) from 11.2 to 17.3 GHz, at the power consumption of 9.93 mW. The free-running oscillation frequency is 3.8 GHz. The die area is 0.644 × 0.908 mm2

    中文摘要 I Abstract III 致謝 V Table of Contents VI List of Figure IX List of Tables XVI Chapter 1 Introduction 1 1.1 Background 1 1.2 Research Motivation 2 1.3 Thesis Organization 5 Chapter 2 Principles and Design Considerations of Oscillators 7 2.1 Introduction 7 2.2 Basic Theory of Oscillators 8 2.3 Feedback Oscillators 9 2.4 The Classification of Oscillators 15 2.4.1 Ring Oscillator 15 2.4.2 LC-Tank Oscillator 19 2.4.3 Parallel RLC-tank 22 2.4.4 Negative-Gm Oscillator 25 2.4.5 Cross-Coupled Oscillator 29 2.5 Inductor 31 2.6 Capacitors 37 2.7 MOSFET Varactors 39 2.7.1 The Accumulation-Mode MOS Capacitor 41 2.7.2 The Inversion-Mode MOS Capacitor 41 2.8 Design Parameters of VCO 42 2.8.1 Quality Factor 42 2.8.2 Definition of Phase Noise 45 2.8.3 Linear Time-Invariant Phase Noise Model 46 2.8.4 Linear Time-Variant Phase Noise Model 50 2.9 Classification of Noise 52 2.9.1 Thermal noise 53 2.9.2 Flicker noise 54 2.9.3 Phase Noise in Communications 55 2.9.4 Models of Phase Noise 57 2.10 Figure of Merit 57 2.11 Design Parameters of VCO 58 Chapter 3 Principles and Design Concepts of Injection Locking Frequency Divider 60 3.1 Principle of Injection Locked Frequency Divider 61 3.2 Locking Range 63 3.3 Example for A Single Injection of ILFD 66 Chapter 4 Wide Locking Range Divide-by-2 Capacitive Cross-coupled Injection-Locked Frequency Divider 68 4.1 Introduction 68 4.2 Circuit Design 69 4.3 Measurement Results and Discussion 71 4.4 Conclusion 76 Chapter 5 Low Power ÷3 Injection-Locked Frequency Divider 77 5.1 INTRODUCTION 77 5.2 Circuit design 78 5.3 EXPERIMENTAL 80 5.4 Conclusion 90 Chapter 6 Low Power Body-Biased Injection-Locked Frequency Divider 91 6.1 INTRODUCTION 91 6.2 Circuit Design 93 6.3 EXPERIMENTAL 93 6.4 Conclusion 99 Chapter 7 Wide-Locking Range Divide-by-4 Injection-Locked Frequency Divider (ILFD) Stacked Divide-by-2 ILFD 101 7.1 INTRODUCTION 101 7.2 Circuit Design 103 7.3 Measurement and Discussion 104 7.4 Conclusion 108 Reference 109

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    [78] S.-L.Jang, and C.-H. Fang, ”Divide-by-4 capacitive cross-coupled injection-locked frequency dividers,” Analog Integr Circ Sig Process.,86:59-63, 2016.
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