在三維積體電路的架構中，將多層的裝置垂直堆疊整合在一起，這樣的架構不僅會不利於散熱，還會使散熱問題更加嚴重，進而使整體電路的可靠度降低。
在本篇論文中，我們提出了考量散熱與可靠度的叢集式三維積體電路的佈局規劃。在佈局規劃中，使用成本函數的方式去平衡整個晶片的面積、線長、功率密度和訊號導通孔的密度之間的關係。並使用修改後的福特富爾克森方法來插入矩形訊號導通孔和雙訊號導通孔，藉以提高導通孔的可靠度。在插入訊號導通孔後，我們建構了一個精確的熱傳導模型來計算溫度分佈。經過溫度分佈的分析計算後，散熱導通孔將被放置稱為導孔通道的預留區域內。散熱導通孔的運行程序將重複運作持續到最高峰溫度降至指定溫度。
實驗結果顯示，我們的架構可以有效地將單一訊號導通孔改善為矩形訊號導通孔或雙訊號導通孔，使用率超過百分之八十以上，整個架構的可靠度大大提升；
此外，我們的所提出以精確的溫度計算熱模型的實驗架構，可以用極少數的散熱導通孔將最高峰溫度降至八十度左右。

In 3D-IC architecture, vertically stacked multiple layer impedes heat dissipation and exacerbates thermal problem especially for reliability degradation.
In this thesis, we propose a cluster-based reliability- and thermal- aware 3D floorplanning with cost function approach to place modules. In this floorplanning, the cost function considers both reliability and thermal factors function with the balance among the chip of area, wire length, power density and density of STSV. Then we insert rectangle-STSVs and double-STSVs for improving reliability by modified Ford-Fulkerson method. After STSV insertion, we construct a precise thermal conduction model to compute temperature distribution in terms of the resultant floorplan. The TTSVs will be inserted at some reserved regions, via-channel, by analytical computation based on temperature distribution. The TTSVs insertion process will repeat until the peak temperature achieved the threshold.
The experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, improving reliability accordingly.
Furthermore, our framework is able to reduce the peak temperature effectively based on a precise temperature computation model.
The temperature can be maintained around 80°C with minimal TTSVs.

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