超寬頻(UWB)是一項可應用於近距離、高速的新興通訊技術，近幾年來更是受到學界和業界的高度青睞。因此，相關的研究變得越來越受歡迎。而本篇論文則著眼於超寬頻應用之射頻前端電路設計。
射頻前端電路在無線通訊接收機中扮演著重要的角色，負責將天線接收下來的微弱訊號放大並維持最小的雜訊為原則。而功率消耗、寬頻輸入阻抗的匹配、雜訊指數和轉換增益都是設計射頻前端電路時的考量因子，然而這些考量因子之間彼此相互衝突所以必須做適當的取捨。在這次的設計中，提出四種不同架構的超寬頻低雜訊放大器和兩種不同架構的射頻前端電路，分別操作於3.1到4.8 GHz和3.1到10.6 GHz的頻帶範圍。
此論文中所設計的晶片皆是使用台灣積體電路製造股份有限公司所提供的0.18微米互補式金氧半導體製程，並且完成所有晶片的製作與量測。

Ultra-wideband (UWB) communication is an emerging technology which has attracted great interests in both academia and industry in the past few years for applications in short-range and high-speed wireless mobile system. Therefore, the correlative researches became more and more popular. In this thesis, the focus of research is to design the RF receiver front-end for UWB applications.
The RF front-end plays an important role in wireless communication receiver and is usually used for amplifying the weak signal after the receiving antenna with minimized noise contribution. Power consuming, broadband input impedance matching, noise figure, and conversion gain, are the major issues to be considered in this design. It is well-known that these issues are trade-offs one another. In our work, the four kinds of UWB low noise amplifier structures and two kinds of UWB front-end structures are designed to cover 3.1 to 4.8 GHz and 3.1 to 10.6 GHz frequency range respectively.
The chip designs are used in TSMC CMOS 1P6M 0.18-um process and completely fabricated and measured.

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