研究生: |
鄭哲安 Che-An Cheng |
---|---|
論文名稱: |
基於模組化設計的快閃記憶體映射管理機制 A Component-based Design for the Address Translation Mechanism of Flash Memory |
指導教授: |
吳晉賢
Chin-Hsien Wu |
口試委員: |
阮聖彰
Shanq-Jang Ruan 林昌鴻 Chang Hong Lin 林淵翔 Yuan-Hsiang Lin |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2015 |
畢業學年度: | 103 |
語文別: | 中文 |
論文頁數: | 46 |
中文關鍵詞: | 快閃記憶體 、快閃記憶體轉換層 |
外文關鍵詞: | NAND Flash Memory, Flash Translation Layers, Embedded Systems, Storage Systems |
相關次數: | 點閱:256 下載:0 |
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隨著非揮發式儲存記憶體的發展,NAND flash memory被廣泛的應用,由於它的小體積、耐震性、高效能與低功耗。但也因為一些NAND flash memory的特性限制與傳統硬碟上的差異。所以快閃記憶體轉換層(Flash Translation Layer,簡稱FTL)就被應用來處理NAND flash memory的特性限制,以便於在不修改檔案系統的前提下能正常的對NAND flash memory進行資料讀寫。針對FTL的討論大致能分成”Address translation”、”Garbage collection”和”Wear-leveling”。 Address translation主要探討資料的讀寫存放位置管理,也是本篇論文的探討重點。本篇論文題出一個模組化的管理機制,利用模組化分析近代具指標性的FTL演算法,藉此以不同角度觀察各個演算法帶給整體系統的效能。
NAND flash memory is a popular memory device because of many advantages such as high-density, light-weight, shock-resistance, non-volatile, and low-power features. Although NAND flash memory has many attractive features, it still has several limitations due to its architectural characteristics. For managing the distinctive characteristics, various flash translation layers (FTLs) have been proposed. The main functions of an FTL contain address translation, garbage collection, and wear-leveling effect. In the thesis, we propose a component-based design for the address translation mechanism of flash memory. The component-based design is based on three features: specificity, composability and analyzability. With the component-based design, it can facilitate developers to realize and redesign the address translation mechanism of flash memory.
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