本論文的主題在於利用硬體仿擬錯誤對動量估測架構的影響，由於VLSI 製程快速演進，使得元件尺寸縮小，造成製造時發生瑕疵的機率上昇，使良率降低，因此如何提升電路的容誤能力 (Error Tolerability) 常是被用來增加晶片有效良率之方法，錯誤 (Fault) 可被區分為不可接受錯誤 (Unacceptable Fault) 以及可接受錯誤 (Acceptable Fault)，如何快速的對錯誤進行分類成為一個需要解決的問題，我們使用現場可程式化閘陣列 (Field Programmable Gate Array) 來實現動量估測架構，在 H.264/AVC 中，動量估測模組約佔 70 % 的運算量，重要性相當高，這也是我們將此模組當作分析目標的原因。在硬體仿擬過程中，我們使用新型的錯誤注入技術將錯誤注入至處理單元陣列 (Processing Element Array) 中，不僅能降低硬體負擔 (Hardware Overhead)，也能加快仿擬的速度。另外我們會去評估錯誤發生時對於整體畫面PSNR的衰減程度，進而分析錯誤對動態向量 (Motion Vector) 的影響。最後在實驗結果中我們可以看到，利用硬體可以讓仿擬過程在毫秒間完成，而且只增加了 3 % 的硬體負擔。

Due to the rapid evolution of VLSI process technologies, the component size is gradually reduced. Therefore, the probabilities of defects occurred during the manufacturing process increase significantly and the yield losses will also increase. Improving the error tolerability of a circuit is considered a promising solution for increasing the effective fabrication yield of the chips. In this thesis, a hardware-based emulation technique is proposed to evaluate the impact of faults for motion estimation architectures. The possible faults of a circuit can be categorized into unacceptable faults or acceptable faults. How to classify the faults with negligible emulation time is a problem that should be dealt with. We use FPGAs (Field Programmable Gate Arrays) to realize the motion estimation architecture. In the H.264/AVC, the motion estimation module is very important since its computational complexity accounts for 70% of the total operations. In the implemented fault emulator, we use a new type of FIE (fault injection element) to inject faults into the processing element array. The proposed FIE can reduce the hardware overhead and speed up the emulation time. In addition, we evaluate the PSNR distortion when the faults occurred in the motion estimation module and then the error tolerability of the circuit can be analyzed. Experimental results show that the emulation can be completed in milliseconds and the hardware overhead is only about 3%.

[1] D. de Andrés, J. C. Ruiz, D. Gil, and P. Gil, “Fault Emulation for Dependability Evaluation of VLSI Systems,” IEEE Trans.VLSI Syst., vol. 16, no. 4, pp. 422-431, Apr. 2008.
[2] C. Y. Lo, H. N. Nham, and A. K. Bose, “Algorithms for an Advanced Fault Simulation System in Motis,” IEEE Trans. on Computer-Aided Design CAD-6, pp. 232-240, March 1987.
[3] M. Butts, J. Batcheller, and J. Varghese, “An Efficient Logic Emulation System,” in Proc. Int’l Conf. on Computer Design (ICCD-92), pp. 138-141, Oct. 1992.
[4] S. Walters, “Computer-Aided Prototyping for ASIC-Based System,” IEEE Design & Test of Computer, pp. 4-10, June 1991.
[5] A. Parreira, J. P. Teixeira, and M. B. Santos, “Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs,” Computing and Informatics, vol. 23, no. 5-6, pp. 1001-1020, 2004.
[6] S. A. Hwang, J. H. Hong, and C. W. Wu, “Sequential Circuit Fault Simulation Using Logic Emulation,” IEEE Trans. Computer-Aided Design, vol. 17, no. 8, pp. 724-736, August 1998.
[7] K. T. Cheng, S. Y. Huang, and W. J. Dai, “Fault Emulation: A New Methodology for Fault Grading,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 10, pp. 1487-1495, Oct. 1999.
[8] A. Ejlali and S. G. Miremadi, “FPGA-Based Fault Injection into Switch-Level Models,” Microprocessors and Microsystems, vol. 28, no. 5-6, pp. 317-327, 2004.
[9] K. T. Cheng, S. Y. Huang, W. J. Dai, “Fault Emulation: A New Approach to Fault Grading,” in Proc. of ICCAD5, pp. 681-686, Nov. 1995.
[10] F. Kocan and D. G. Saab, “Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware,” Journal of Electronic Tesing: Theory and Applications, vol. 23, no.5, pp. 405-420, 2007.
[11] J. H. Hong, S. A. Hwang, and C. W. Wu, “An FPGA-based hardware emulator for fast fault emulation,” in Proc. Midwest Symp. on Circuits and Systems, (Ames), Aug. 1996.
[12] C. Hyukjune and A. Ortega, “Analysis and testing for error tolerant motion estimation,” in Proc. IEEE Int’l Symp. On Defect and Fault Tolerance in VLSI Systems, pp. 514-522, Oct. 2005.
[13] H. Y. Cheong, et al., “Computation Error Tolerance in Motion Estimation Algorithms,” in Proc. IEEE Int’l Conf. on Image Processing, pp. 3289-3292, Oct. 2006.
[14] C. In Suk and A. Ortega, “Hardware testing for error tolerant multimedia compression based on linear transforms,” in Proc. IEEE Int’l Symp. On Defects and Fault Tolerance in VLSI Systems, pp. 523-531, Oct. 2005.
[15] Video Codec for Audiovisual Services at p × 64 Kbit/s, ITU-T Recommendation H.261, Mar. 1993.
[16] Information Technology-Generic Coding of Moving Pictures and Associated AudioInformation: Video, ISO/IEC 13818-2 and ITU-T Recommendation H.262, 1996.
[17] Video Coding for Low Bit Rate Communication, ITU-T Recommendation H.263, Feb. 1998.
[18] Joint Video Team, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Recommendation H.264 and ISO/IEC 14496-10 AVC, May. 2003.

[19] Information Technology-Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbit/s - Part 2: Video, ISO/IEC 11172-2, 1993.
[20] Information Technology-Coding of Audio-Visual Objects - Part 2: Visual, ISO/IEC 14496-2, 1999.
[21] http://trace.eas.asu.edu/index.html
[22] Iain. E. G. Richardson, H.264 and MPEG-4 Video Compression, 2003.
[23] H. G. Musmann, P. Pirsch, and H. J. Grallert, “Advances in picture coding,” Proc. IEEE, vol. 73, pp. 523-548, Apr. 1985.
[24] T. Koga et al., “Motion-compensated interframe coding for video conferencing,” in Proc. Nat. Telecommunications Conf., pp. G 5.3.1-G 5.3.5, Nov. /Dec. 1981.
[25] J. R. Jain and A. K. Jain, “Displacement measurement and its application in interframe image coding,” IEEE Trans. Commun., vol. COM-29, pp. 1799-1808, Dec. 1981.
[26] R. Srinivasan and K. R. Rao, “Predictive coding based on efficient motion estimation,” IEEE Trans. Commun., vol. COM-33, pp. 1011-1014, Sept. 1985.
[27] S. Zhu and K. K. Ma, “A new diamond search algorithm for fast block matching motion estimation,” in Proc. Int. Conf. Inform., Commun., Signal Process., Singapore, pp. 292-296, Sept. 9-12, 1997.
[28] K. M. Yang, M. T. Sun, and L. Wu, “A family of VLSI designs for the motion compensation block-matching algorithm,” IEEE Trans. on Circuits and Systems, vol. 36, no. 2, pp. 1317-1325, Oct. 1989.
[29] H. Yeo and Y. H. Hu, “A novel modular systolic array architecture for full-search block matching motion estimation,” IEEE Trans. Circuits and Systems for Video Technology, vol. 5, no. 5, pp. 407-416, Oct. 1995.

[30] Y. K. Lai and L. G. Chen, “A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm,” IEEE Trans. Circuits and Systems for Video Technology, vol. 8, no. 2, pp. 124-127, Apr. 1998.
[31] T. Komarek and P. Pirsch, “Array architectures for block matching algorithms,” IEEE Trans. Circuits and Systems, vol. 36, no. 2, pp. 1301-1308, Oct. 1989.
[32] L. D. Vos and M. Stegherr, “Parameterizable VLSI architectures for the fullsearch block-matching algorithm,” IEEE Trans. on Circuits and Systems, vol. 36, no. 2, pp. 1309-1316, Oct. 1989.
[33] C. H. Hsieh and T. P. Lin, “VLSI architecture for block-matching motion estimation algorithm,” IEEE Trans. Circuits and Systems for Video Technology, vol. 2, no. 2, pp. 169-175, Jun. 1992.
[34] Quick-Turn Design System Inc., “MARSIII Emulation System User’s Guide”, Mountain View, California, Jan. 1994.
[35] López-Ongil et al. “Autonomous Fault Emulation: A New FPGA-based Acceleration System for Hardness Evaluation,” IEEE Trans. on Nuclear Science, vol. 54, Issue1, Part 2, pp. 252-261, Feb. 2007.
[36] P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and M. Violante, “FPGA-based fault injection techniques for fast evaluation of fault tolerante in VLSI circuits,” in Proc. Forum on Programmable Logic (FPL), Belfast, Northern Ireland, Aug. 2001.
[37] S. K. Lu, Y. M. Chen, and S. Y. Huang, “Speeding-up Emulation-Based Diagnosis Techniques for Logic Cores,” IEEE Design and Test of Computers, pp. 88-97, July-August, 2011.