研究生: |
李振元 CHEN-YUAN LEE |
---|---|
論文名稱: |
應用於筆記型電腦之二相式直流/直流轉換器研製 Study and Implementation of a Two-Phase Interleaved DC/DC Converter for Notebook PCs |
指導教授: |
羅有綱
Yu-Kang Lo |
口試委員: |
邱煌仁
Huang-Jen Chiu 劉益華 Yi-Hua Liu |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 中文 |
論文頁數: | 75 |
中文關鍵詞: | 電壓調節模組 、多相式降壓型同步整流轉換器 、暫態響應 |
外文關鍵詞: | Voltage Regulator Module, multi-phase synchronous buck converter, transient response |
相關次數: | 點閱:660 下載:15 |
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筆記型電腦的電壓調節模組(Voltage Regulator Module,VRM)必須提供高電流輸出、快速的暫態響應,並滿足Intel獨有的直流負載線(DC Load Line)設計,但又常常受到「輕薄短小」的機構限制。在這樣特有的條件之下,如何設計一個高效率,兼具低成本的電力轉換器,對於所有電源工程師來說,是一致的追求目標。
多相式降壓型同步整流轉換器普遍應用於中央處理器的電力轉換設計,其原因不外乎該轉換器擁有高轉換效率、低輸出電壓漣波、與快速暫態響應的特性,因此無須為了改善暫態響應與電壓漣波,而對轉換效率做任何妥協。
本論文研究一種應用於筆記型電腦的二相式降壓型同步整流轉換器,在功率級的部份採用二相各交錯 導通的降壓型轉換器,得以有效降低電壓漣波,並減少輸出入電容的使用數量。在變載暫態時控制器將提高切換頻率,不致造成突然的電壓驟降,而超出中央處理器應有的電壓調節率與直流負載線。經驗證實作之電力轉換器,其性能與設計目標一致,結果令人滿意。
A voltage regulator module (VRM) for notebook PCs is required to provide high output current and fast transient response. Most of all, the DC load line design uniquely specified by the Intel Corp. must be met, while constrained by the limited dimensions. It is a tough task for every power supply engineer to design a high- efficiency and low-cost power converter under these conditions.
A multi-phase synchronous buck converter is commonly adopted for a CPU power supply due to its high conversion efficiency, low output voltage ripple and fast transient response. The fast transient response and low voltage ripple can be achieved without sacrificing the conversion efficiency.
The main focus of this thesis is to study and implement a two-phase synchronous buck converter used in notebook PCs. The power stage consists of two interleaved buck converters operated with 180 phase difference to effectively reduce the voltage ripple and the number of input and output capacitors. The switching frequency is increased during the transient period to prevent any sudden voltage drop from exceeding CPU’s voltage tolerance and violating the DC load line design rule. Satisfactory experimental results have demonstrated that the implemented two-phase interleaved synchronous buck converter is able to meet the specifications.
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