本文旨在研製三相功率轉換器併聯系統。本系統三相功率轉換器採用三階層架構，以減少輸出電壓之諧波。第一組三相三階層功率轉換器為電壓控制型功率轉換器，利用電壓閉迴路控制，以提供一穩定且低諧波失真之三相平衡電源，供給負載。併聯之第二組三相三階層功率轉換器為電流控制型功率轉換器，利用電流閉迴路控制，且依據功率分配表輸出所選擇之功率狀態，達成功率轉換器併聯控制及分攤負載功率之目的。
本文已建立功率轉換器之數學模型，並利用座標系統轉換，推導出電壓閉迴路控制與電流閉迴路控制策略，以提供併聯系統之控制。在實體製作方面，採用數位信號處理器(DSP, TMS320F2812)為系統控制核心，並搭配可程式邏輯元件(CPLD, XC9536)，以減少硬體電路元件，完成整體系統之實體製作。
實測方面，單組功率轉換器之滿載功率為 ，總諧波失真率為 ；併聯控制方面，已完成二組 之併聯系統，並利用均流之策略，當二組同時併聯運轉時，其負載量均為負載之一半；且為使併聯系統之可靠度增加，使用主-僕式控制策略，增加系統之可靠度。

This thesis presents the development of parallel three-phase inverter systems. In the three-phase inverter system, the three-level switching is designed to reduce the output voltage harmonics. The first power inverter is operated at voltage-controlled mode which uses voltage closed-loop control to provide stable and low-harmonic ac voltage source to load, while the second parallel power inverter is operated under current-controlled mode which uses current closed-loop control to supply the power in accordance with the build-in power-distribution list, and thereby achieves paralleling control and load-sharing.
In this thesis, the digitized mathematical models are built. The strategies of voltage and current closed-loop controls using the coordinate transformation are inferred. Then, a high-performance, low-cost digital signal processor (DSP, TMS320LF2812) and complex programmable logic device (CPLD, XC9536) is used to implement the system for reducing the circuit components and cost.
Experimental result for single power inverter yields the full-load power of 750W with voltage harmonic distortion of . Whereas, with 1kW parallel controlled system, each power inverter loads half of the output load power by using the strategy of balanced current sharing. In order to increase the reliability, master-slave control technique is used.

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