本論文提出應用於5G的基於多路線連續消除演算法極化碼(Polar Code)解碼器，超大型積體電路(VLSI)設計與實現，在硬體架構上以設計多種碼率及碼長，以及降低面積為主要目標。
其中運算參數及主要參考文獻，以華為(Huawei)在IEEE Xplore以及第三代合作夥伴計劃（3rd Generation Partnership Project，3GPP）會議當中提出的論文為基礎。並且軟體模擬結果以及硬體設計結果，都以華為(Huawei)、三星(Samsung)和Tsofun Algorithm等公司在3GPP會議中提出之數據為參考基礎，作為設計驗證的依據。本論文軟體使用的模擬環境為C以及MATLAB，使用的FPGA模擬環境為Xilinx Zedboard Zynq-7000，而設計電路之實現則是使用TSMC 90nm CMOS製程技術進行實作，硬體架構以減少面積為目標，並且根據3GPP所訂出之標準，可靠度達到99.999%。最後將完成的各項數據表現與比對以及未來展望作為本文的結論。

This thesis proposes the design and implementation of multi-list successive cancellation polar decoder for fifth generation (5G). The purpose of the design is configurable code rate, code length and reducing area of chip.
The parameters and main references are based on the papers which are proposed by Huawei in IEEE Xplore and 3rd generation partnership project (3GPP) conference. The design verifications of software simulations and hardware design are based on papers proposed by Huawei, Samsung, Tsofun Algorithm and other companies in the 3GPP conference. The software simulation environment of this thesis is C and MATLAB, the FPGA verification environment is Xilinx Zedboard Zynq-7000, and the implementation of the circuit using a TSMC 90nm CMOS technology. Our goal is to reduce the area of hardware architecture and let the reliability have to reach 99.999% under the standards which is proposed by 3GPP. Finally, the performance and future prospects are the conclusion of this thesis.

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