正交分頻多工調變（Orthogonal Frequency Division Multiplexing，OFDM）因為具有節省傳輸頻寬和抵抗符元間干擾（InterSymbol Interference，ISI）的優點，所以被普遍使用於許多新一代的通訊標準中。快速傅立葉轉換（Fast Fourier Transform，FFT）處理器是OFDM系統中的關鍵部分。為了實現出一個能適用於各種通訊標準的可變長度FFT處理器，本篇論文以記憶體式（Memory Based）架構和Mixed Radix演算法做為處理器的設計基礎。除了引用某些文獻的方法降低處理器硬體複雜度，本篇論文也修改了原先的記憶體式架構。利用交替記憶體對週邊使用權的方式達到如同管線式（Pipline）FFT處理器般的連續資料流輸出，接著提出一種資料存取策略使得FFT處理器的輸出入都是正常次序。最後進行處理器的整體效能評估，並驗證其可行性。

　　Orthogonal Frequency Division Multiplexing (OFDM) has been adopted in new generation communication standards because it can save transmission bandwidth and reduce InterSymbol Interference (ISI). Fast Fourier Transform (FFT) processor is the most important part in the OFDM system. In order to satisfy various kinds of communication application standards, a variable length FFT processor should be designed, Memory Based structure and Mixed Radix algorithm as the foundations of designing processor are established. In addition to low complexity hardware design technique, this thesis also modified the old kind of Memory Based architecture. We take advantage of altering memory access right to peripheral to achieve continuous data flow output like Pipelined FFT processor, and then develop a strategy for data access to ensure the sequences of the FFT processor in/output are normal order. At last we assess the entire performance of the processor, and verify its feasibility.

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