簡易檢索 / 詳目顯示

回結果列表
研究生： 莊昀學
Yun-Hsueh Chuang
論文名稱： 新式互補式金氧半壓控振盪器與注入鎖定除頻器之設計
Design of Novel CMOS Voltage Controlled Oscillators and Injection Locked Frequency Dividers
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 莊敏宏
Miin-Horng Juang
陳凰美
none
學位類別： 博士
Doctor
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 142
中文關鍵詞： 壓控振盪器 、注入鎖定除頻器
外文關鍵詞： VCO, ILFD
相關次數： 點閱：185  下載：1 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  •  上一筆

    • 壓控振盪器與除頻器是頻率合成器電路中，主要的電路之一。對壓控振盪器而言，低相位雜訊可避免相鄰雜訊訊號經由混波轉換的干擾。而振盪器的輸出則經由除頻器來達成降頻的工作，因此，除頻器需具有高頻操作，寬的操作頻寬及低功率消耗。
    首先，本論文呈現二個以抽頭電感技術所設計之操作在4 GHz 頻帶LC-tank差動壓控振盪器，在1 MHz偏移頻率下，此振盪器具有低於-120 dBc/Hz的相位雜訊表現。接著一個具有寬調變頻率的環形振盪器亦實現，其調變範圍超過70%，但受限於先天的特性，其相位雜訊明顯低於LC-tank振盪器。雖然環形振盪器的相位雜訊較差，但利用其它的特點，若應用於注入鎖定除頻器，卻有較佳的效果。
    其次，我們呈現利用直接注入鎖定技術之注入鎖定除頻器電路，注入鎖定技術可達到高頻操作及低功率損耗的功能。第一個電路採用LC振盪器為主的注入鎖定除頻器可操作在0.75 V 電壓，在注入信號為0dBm時，此除頻器具有由3.27GHz至4.64GHz之頻率鎖定範圍。另外兩個注入鎖定除頻器電路則以環形振盪器為基礎，分別利用可切換電容負載電路與可調變電感負載電路來達成寬注入鎖定範圍的功能。前者具有從1.95 GHz 到5.5 GHz的注入鎖定範圍，而後者則具有從1.15 GHz 到 7.4 GHz的注入鎖定範圍。
    最後，一個利用變壓器耦合技巧之新式四相位壓控振盪器亦呈現，此新式四相位壓控振盪器在0.7V 電壓下，其輸出之相位雜訊在距離2.4GHz載波頻率1MHz處所量測之結果可達-124.9dBc/Hz，其調諧範圍為135MHz。

    The key building blocks in the frequency synthesizer are the voltage controlled oscillator (VCO) and the high frequency divider circuit. Most importantly, low phase-noise is required to avoid corrupting the mixer-converted signal by close interfering tones for VCO circuit. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption.
    First, this thesis describes two differential VCOs with tapped inductors. Both of two VCOs operate at a 4 GHz band with good phase noise lower than -120 dBc/Hz at 1MHz offset frequency. Also, a wide tuning range ring oscillator is presented. This circuit has a wide tuning range up to 70%, but its phase noise is worse than the LC-tank oscillator due to its inherent characteristic.
    Then the injection locking technique is applied in high speed, low power frequency dividers, namely injection locked frequency dividers (ILFDs). Based on this technique, three ILFDs are presented for wide locking range application. The LC-tank oscillator ILFD can operate at 0.75 V supply voltage with a locking range from 3.14 GHz to 4.63 GHz while 0 dBm incident power is applied. The two ring oscillator based ILFDs which use switched capacitor load and variable inductor load respectively can provide a very wide locking range. The former has a locking range from 1.95 GHz to 5.5 GHz and the latter is from 1.15 GHz to 7.4GHz.
    Finally, a novel quadrature VCO (QVCO) is proposed. By using transformer feedback technique, it can achieve lower phase noise performance about -124 dBc/Hz at 2.4GHz band with 135 MHz tuning range while 0.7 V supply voltage is applied.

    中文摘要 I ABSTRACT III 誌謝 IV TABLE OF CONTENTS V LIST OF FIGURES VII LIST OF TABLES XI CHAPTER ONE INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER TWO OVERVIEW OF THE VOLTAGE-CONTROLLED OSCILLATORS 5 2.1 INTRODUCTION 5 2.2 PRINCIPLE OF OSCILLATION 6 2.2.1 FEEDBACK MODEL 7 2.2.2 ONE-PORT VIEW 8 2.3 CLASSIFICATION OF OSCILLATORS 11 2.3.1 RING OSCILLATOR 11 2.3.2 LC-TANK OSCILLATOR 13 2.4 DESIGN CONSIDERATIONS OF VOLTAGE CONTROLLED OSCILLATOR 15 2.5 PHASE NOISE IN OSCILLATOR 18 2.5.1 PHASE NOISE DEFINITION 18 2.6 PARALLEL RLC TANK 24 2.6.1 QUALITY FACTOR 25 2.6.2 INDUCTOR DESIGN 27 2.6.3 TRANSFORMER DESIGN [14] 33 2.6.4 VARACTOR DESIGN 40 CHAPTER THREE DESIGN OF DIFFERENTIAL VOLTAGE CONTROLLED OSCILLATOR 45 3.1 TAPPED INDUCTOR DESIGN 46 3.2 PROPOSED DIFFERENTIAL HARTLEY OSCILLATOR 47 3.2.1 DESIGN CONCEPT AND OPERATION OF HARTLEY VCO 47 3.2.2 MEASURED RESULTS AND DISCUSSIONS 53 3.3 PROPOSED DIFFERENTIAL CROSS-COUPLED OSCILLATOR 56 3.3.1 DESIGN PRINCIPLE OF DIFFERENTIAL VCO USING TAPPED INDUCTOR 56 3.3.2 MEASURED RESULTS AND DISCUSSIONS 61 3.4 WIDE TUNING RANGE RING OSCILLATOR DESIGN 64 3.4.1 CIRCUIT DESIGN OF THE RING OSCILLATOR 64 3.4.2 MEASURED RESULTS AND DISCUSSIONS 67 3.5 SUMMARY 69 CHAPTER FOUR DESIGN OF INJECTION LOCKED FREQUENCY DIVIDER 71 4.1 PRINCIPLE OF INJECTION LOCKED DIVIDER 72 4.1.1 LOCKING RANGE 74 4.2 LOW VOLTAGE LC-TANK OSCILLATOR ILFD DESIGN 76 4.2.1 CONVENTIONAL LC-TANK OSCILLATOR ILFD 76 4.2.2 PROPOSED LOW VOLTAGE LC-TANK OSCILLATOR ILFD DESIGN 80 4.2.3 MEASURED RESULTS AND DISCUSSIONS 83 4.3 WIDE BAND ILFD WITH SWITCHED CAPACITOR LOAD 86 4.3.1 PROPOSED ILFD WITH SWITCHED CAPACITOR LOAD DESIGN 86 4.3.2 MEASURED RESULTS AND DISCUSSIONS 90 4.4 WIDE BAND ILFD WITH VARIABLE INDUCTOR LOAD 95 4.4.1 PROPOSED ILFD WITH VARIABLE INDUCTOR LOAD DESIGN 95 4.4.2 MEASURED RESULTS AND DISCUSSIONS 100 4.5 SUMMARY 103 CHAPTER FIVE A QUADRATURE VOLTAGE CONTROLLED OSCILLATOR BASED ON TRANSFORMER FEEDBACK 104 5.1 TRADITIONAL QVCO DESIGN 105 5.2 PROPOSED TRANSFORMER FEEDBACK QVCO DESIGN 109 5.2.1 THE NOVEL LOW VOLTAGE QVCO DESIGN 110 5.2.2 MEASURED RESULTS AND DISCUSSIONS 114 5.3 EXTENSION OF PROPOSED QVCO TOPOLOGY 118 5.4 SUMMARY 119 CHAPTER SIX CONCLUSIONS 121 REFERENCES 124 PUBLICATIONS 129

    [1] N. M. Nguyen, and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuits, vol. 27, pp. 810-820, May 1992.
    [2] S. Smith, “Microelectronic Circuit 4th edition,” Oxford University Press 1998.
    [3] B. Razavi, “RF Microelectronics,” Upper Saddle River, NJ: Prentice Hall, 1998.
    [4] B. Razavi, “Design of Analog CMOS Integrated Circuits,” Mc Graw Hill, 2001.
    [5] J. J. Rael, and A. A. Abidi, “Physical processes of phase Noise in differential LC Oscillators,” IEEE Custom Integrated Circuits Conference, pp. 569-572, 2000.
    [6] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
    [7] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329-330, Feb. 1966.
    [8] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
    [9] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999.
    [10] T. H. Lee, “The design of CMOS radio frequency integrated circuits,” Cambridge University Press 1998.
    [11] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, pp. 101-109, Jun 1974.
    [12] J. Craninckx and M. S. J. Steyaert, “A 1.8 GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 736-744, May 1997.
    [13] P. Yue, C. Ryu, J. Lau, T. Lee, and S. Wong, “A physical model for planar spiral inductors on silicon,” 1996 International Electron Devices Meeting Technical Digest, pp. 155-158, Dec. 1996.
    [14] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
    [15] E. Frlan, S. Meszaros, M. Cuhaci, and J.Wight, “Computer-aided design of square spiral transformers and inductors,” IEEE MTT-S, Microwave Symposium Digest, pp. 661-664, June 1989.
    [16] M. W. Geen, G. J. Green, R.G. Arnold, J. A. Jenkins, and R. H. Jansen, “Miniature multilayer spiral inductors for GaAs MMICs,” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, pp. 303-306, Oct. 1989.
    [17] A. Kiranas and Y. Papanaos, “Design issues towards the integration of passive components in silicon RF VCOs,” IEEE International Conference on Electronics, Circuits and Systems, vol. 2, pp. 311-314, Sept. 1998.
    [18] P. Andreani, and S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
    [19] A. Hajimiri and T. H. Lee, “The design of low noise oscillators,” Norwell, MA: Kluwer, 1999.
    [20] R. Aparicio and A. Hajimiri, “A noise-shifting differential Colpitts VCO,” IEEE J. Solid-State Circuits, vol. 12, no. 12, pp. 1728-1736, Dec. 2002.
    [21] K. O. Kenneth, N. Park, and D. J. Yang, “1/f noise of nMOS and pMOS transistors and their implications to design of voltage controlled oscillators,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 59-62, Jun. 2002.
    [22] G. De Astis, D. Cordeau, J. M. Paillot, and L. Dascalescu, “A 5-GHz fully integrated full PMOS low-phase-noise LC VCO,” IEEE J. Solid-State Circuits, vol. 40, no. 10, pp.2087-2091, Oct. 2005.
    [23] T. Song, S. Ko, D. H. Cho, H. S. Oh, C. Chung, and E. Yoon, “A 5 GHz transformer- coupled shifting CMOS VCO using bias-level technique,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.127-130, June 2004.
    [24] P. W. Lai, L. Dobos, and S. Long, "A 2.4GHz SiGe low phase-noise VCO using on chip tapped inductor," IEEE European Solid State Circuits Conference (ESSCIRC), pp. 505-508, Sept. 2003.
    [25] A. Jerng, and C. G. Sodini, “The impact of device type and sizing on phase noise mechanisms,” IEEE J. Solid-State Circuits, vol. 40, pp. 360–369, 2005.
    [26] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
    [27] W. S. T. Yan, and H. C. Luong, “A 900-MHz CMOS low-phase-noise voltage- controlled ring oscillator,” IEEE Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, pp. 216-221, Feb. 2001.
    [28] N. Retdian, S. Takagi, and N. Fujii, “Voltage controlled ring oscillator with wide tuning range and fast voltage swing,” IEEE Asia-Pacific Conference, pp. 201-204, Aug. 2002.
    [29] M. D. Tsai, Y. H. Cho, and H. Wang, “A 5-GHz low phase noise differential colpitts CMOS VCO,” IEEE Microwave Wireless Component Letter, vol. 15, pp. 327- 329, May 2005.
    [30] C. M. Hung, B. Floyd, and K. K. O, “A fully integrated 5.35-GHz CMOS VCO and a prescaler,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 17-22, Jan. 2001.
    [31] S. S. Lu, T. Wang, and Y. S. Lin, “High-performance fully integrated 4 GHz CMOS LC VCO in standard 0.18-um CMOS technology,” Emerging Information Technology Conference, pp. 1-4, Aug. 2005.
    [32] K. Stadius, and K. Halonen, “Development of 4-GHz flip-chip VCO module,” IEEE International Symposium on Circuit and System (ISCAS), vol. 3, pp. 2687-2690, May 2005.
    [33] J. Maget, M. Tiebout, and R. Kraus, “Influence of Novel MOS Varactors on the Performance of a Fully Integrated UMTS VCO in Standard 0.25-um CMOS Technology,” IEEE J. Solid-State Circuits, vol. 37, pp. 953-958, July 2002.
    [34] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
    [35] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
    [36] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
    [37] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
    [38] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
    [39] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
    [40] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
    [41] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
    [42] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
    [43] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
    [44] H. Wu, “Signal generation and processing in high-frequency/high-speed silicon- based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
    [45] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
    [46] R. L. Miller, “Fractional-frequency generators utilizing regenerative modulation,” in Proc. Inst. Radio Eng. (IRE), pp. 446–457, July 1939.
    [47] A. Mazzanti, P. Uggetti, and F. Svelto, “Analysis and design of injection-locked LC dividers for quadrature generation,” IEEE J. Solid-State Circuits, vol. 39, pp. 1425-1433, Sept. 2004.
    [48] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, pp. 1170-1174, July 2004.
    [49] H. R. Rategh, H. Samavati, and T.H. Lee, “A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider,” IEEE Custom Integrated Circuits Conf. (CICC), pp. 517-520, May 1999.
    [50] K. Kwok, and H. C. Luong, “A 0.35-V 1.46-mW low-phase-noise oscillator with transformer feedback in standard 0.18-um CMOS process,” IEEE Custom Integrated Circuits Conf. (CICC), pp. 551-554, Sept. 2003
    [51] K. Yamamoto, T. Norimatsu and M. Fujishima, “High-speed and wide-tuning-range LC frequency dividers,” IEEE International Symposium on Circuit and System (ISCAS), pp. 361-364, May 2004.
    [52] A. Tedesco, A. Bonfanti, L. Panseri, and A. Lacaita, “A 11-15GHz CMOS 2 Frequency divider for broad-band I/Q generation,” IEEE Microwave Wireless Component Letter, vol. 15, pp. 724-726, Nov. 2005.
    [53] L. H. Lu, J. C. Chien, “A wide-band CMOS injection-locked ring oscillator,” IEEE Microwave Wireless Component Letter, vol. 15, pp. 676-678, Oct. 2005.
    [54] J. Van der Tang , P. van de Ven, D. Kasperkovsky, and A. van Roermund, “Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator,” IEEE J. Solid State Circuits, vol. 37, pp. 657-661, May 2002.
    [55] B. Razavi, “RF transmitter architectures and circuits,” IEEE Custom Integrated Circuits Conf. (CICC), pp. 197-204, May 1999.
    [56] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, pp. 873-887, June 2001.
    [57] J. P. Maligeorgos, and J. R. Long, “A low-voltage 5.1-5.8 GHz image-reject receiver with wide dynamic range,” IEEE J. Solid-State Circuits, vol. 35, pp. 1917-1926, Dec. 2000.
    [58] A. Mazzanti, P. Uggetti, P. Rossi, and F. Svelto, “Injection locking LC dividers for low power quadrature generation,” IEEE Custom Integrated Circuits Conf. (CICC), pp. 563-566, Sept. 2003.
    [59] A. Rofougaran, G. Chang, J.J. Rael, J.Y. Chang, M. Rofougaran, P.J. Chang, M. Djafari, M. Ku, E.W. Roth, A. Abidi, and H. Samueli, “A single-chip 900-MHz spread-spectrum wireless transceiver in 1-um CMOS-Part I: Architecture and transmitter design,” IEEE J. Solid-State Circuits, vol. 33, pp. 515-534, Apr. 1998.
    [60] P. Andreani, “A low-phase-noise, low-phase-error 1.8 GHz quadrature CMOS VCO,” IEEE ISSCC Dig. Tech. Papers, pp. 290-291, Feb. 2002.
    [61] J. Cabanillas, L. Dussopt, J. M. L. Villegas, and G. M. Rebeiz, “A 900 MHz low phase noise CMOS quadrature oscillator,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 63-66, June 2002.
    [62] S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi, “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE J. Solid-State Circuits, vol. 38, pp. 1148-1154, July 2003.
    [63] W. Jian, T. Jun, and W. Omar, “Theory of cross-coupled RF oscillator for multi- and quadrature-phase signal generation,” ASIC, 2003. Proceed. 5th Int.l Conf., vol. 2, pp. 1014-1017, Oct. 2003.
    [64] A. M. ElSayed and M. I. Elmasry, “Low-phase-noise LC quadrature VCO using coupled tank resonators in a ring structure,” IEEE J. Solid-State Circuits, vol. 36, pp. 701-705, Apr. 2001.
    [65] M. Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1018-1024, July 2001.
    [66] D. Leenaerts, C. Dijkmans, and M. Thompson, “A 0.18 µm CMOS 2.45 GHz low-power quadrature VCO with 15% tuning range” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 67-70, June 2002.
    [67] H. R. Kim, C. Y. Cha, S. M. Oh, M. S. Yang, and S. G. Lee, “A very low-power quadrature VCO with back-gate coupling,” IEEE J. Solid-State Circuits, vol. 39, pp. 952-955, June 2004.
    [68] A. W. L. Ng and H. C. Luong, “A 1V 17GHz 5mW Quandrature CMOS VCO based on transformer coupling,” IEEE ISSCC Dig. Tech. Papers, pp. 711-720, Feb. 2006.

    無法下載圖示 全文公開日期 2009/01/12 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 2009/01/12 (國家圖書館：臺灣博碩士論文系統)
    QR CODE