本論文提出應用於5G 行動通訊的低密度奇偶檢查碼(LDPC)解碼器超大型積體電路(VLSI)設計，以基於LDPC NMSA的共享參數神經網路解碼演算法做為基礎，進行訓練方式的改良，訓練方式則使用限制校正因子參數的訓練範圍，使得模型驅動的神經網路符合LDPC模型架構，進而增加其解碼效能，在迭代方面則可以提升效能達到減少迭代次數的目的，在模擬演算法效能時，可以得知當SNR為5dB時，BER的解碼效能相較[6]約有7.13dB的效能提升。
本論文演算法使用的軟體模擬環境為Python以及MATLAB ，在硬體設計上則使用Vivado進行RTL coding的撰寫以及電路合成，而晶片設計採用TSMC 40nm CMOS製程技術進行實作。

This paper presents a Very Large-Scale Integration (VLSI) design of a Low-Density Parity-Check (LDPC) decoder for application in 5G mobile communication. The design is based on a neural network decoding algorithm utilizing LDPC Normalized Min-Sum Algorithm (NMSA) and incorporates improvements in the training methodology. The training process employs restricted correction factor parameter ranges to ensure that the model-driven neural network aligns with the LDPC model structure, thereby enhancing its decoding performance. Additionally, the iterative process is optimized to reduce the number of iterations and achieve improved performance. Simulating the algorithm's performance reveals that at a Signal-to-Noise Ratio (SNR) of 5dB, the Bit Error Rate (BER) decoding performance is approximately 7.13dB better compared to [6].
The software simulation environment employed in this paper utilizes Python and MATLAB. For hardware design, RTL coding is carried out using Vivado, followed by circuit synthesis. The chip design is implemented using TSMC's 40nm CMOS fabrication process technology.

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